PIC18F67J90-I/PT Microchip Technology, PIC18F67J90-I/PT Datasheet
PIC18F67J90-I/PT
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PIC18F67J90-I/PT Summary of contents
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... Microcontrollers with LCD Driver © 2009 Microchip Technology Inc. PIC18F87J90 Family Data Sheet 64/80-Pin, High-Performance and nanoWatt Technology Preliminary DS39933C ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Allows for safe shutdown if peripheral clock fails Flash SRAM Program Data Device Memory Memory (Bytes) (Bytes) PIC18F66J90 64K 3,923 PIC18F67J90 128K 3,923 PIC18F86J90 64K 3,923 PIC18F87J90 128K 3,923 © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Peripheral Highlights: • High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC) • ...
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... In-Circuit Debug via Two Pins • Operating Voltage Range: 2.0V to 3.6V • 5.5V Tolerant Input (digital pins only) • Selectable Open-Drain Configuration for Serial Communication and CCP Pins for Driving Outputs • On-Chip 2.5V Regulator Preliminary © 2009 Microchip Technology Inc. ...
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... V /V DDCORE CAP 10 RF7/AN5/SS/SEG25 11 RF6/AN11/SEG24/C1INA 12 RF5/AN10/CV /SEG23/C1INB REF 13 RF4/AN9/SEG22/C2INA 14 RF3/AN8/SEG21/C2INB 15 RF2/AN7/C1OUT/SEG20 16 Note 1: The CCP2 pin placement depends on the CCP2MX bit setting. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY PIC18F66J90 PIC18F67J90 Preliminary 50 49 RB0/INT0/SEG30 48 RB1/INT1/SEG8 47 RB2/INT2/SEG9/CTED1 46 RB3/INT3/SEG10/CTED2 45 RB4/KBI0/SEG11 44 RB5/KBI1/SEG29 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI/RA7 39 V ...
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... RF3/AN8/SEG21/C2INB 17 RF2/AN7/C1OUT/SEG20 18 RH7/SEG43 19 RH6/SEG42 Note 1: The CCP2 pin placement depends on the CCP2MX bit setting. DS39933C-page PIC18F86J90 PIC18F87J90 Preliminary RJ2/SEG34 59 RJ3/SEG35 58 RB0/INT0/SEG30 57 RB1/INT1/SEG8 56 RB2/INT2/SEG9/CTED1 55 RB3/INT3/SEG10/CTED2 54 RB4/KBI0/SEG11 53 RB5/KBI1/SEG29 52 RB6/KBI2/PGC OSC2/CLKO/RA6 OSC1/CLKI/RA7 RB7/KBI3/PGD RC5/SDO/SEG12 46 RC4/SDI/SDA/SEG16 45 RC3/SCK/SCL/SEG17 44 RC2/CCP1/SEG13 43 RJ7/SEG36 42 RJ6/SEG37 © 2009 Microchip Technology Inc. ...
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... Packaging Information.............................................................................................................................................................. 421 Appendix A: Revision History............................................................................................................................................................. 427 Appendix B: Migration From PIC18F85J90 to PIC18F87J90 ............................................................................................................ 427 The Microchip Web Site ..................................................................................................................................................................... 439 Customer Change Notification Service .............................................................................................................................................. 439 Customer Support .............................................................................................................................................................................. 439 Reader Response .............................................................................................................................................................................. 440 Product Identification System ............................................................................................................................................................ 441 © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Preliminary DS39933C-page 5 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39933C-page 6 Preliminary © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F66J90 • PIC18F86J90 • PIC18F67J90 • PIC18F87J90 This family combines the traditional advantages of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – with a versatile on-chip LCD driver, while maintaining an extremely competitive price point ...
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... SEGs x 4 COMs) can be driven by 80-pin devices. All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. The pinouts for all devices are listed in Table 1-3 and Table 1-4. Preliminary © 2009 Microchip Technology Inc. RAM for both ...
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... SEGs x 4 COMs Yes Yes 2 MSSP, Addressable USART, Enhanced USART 12 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set enabled 80-Pin TQFP Preliminary PIC18F67J90 128K 65,536 3,923 PIC18F87J90 128K 65,536 3,923 DS39933C-page 9 ...
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... Reset ALU<8> Timer (3) LVD SS MCLR ADC Timer3 CTMU 10-bit EUSART RTCC MSSP Preliminary PORTA (1,2) RA0:RA7 12 PORTB (1) RB0:RB7 4 Access Bank 12 PORTC (1) RC0:RC7 PORTD (1) RD0:RD7 8 PORTE PRODL RE0:RE1, (1) RE3:RE7 PORTF 8 (1) RF1:RF7 8 PORTG (1) RG0:RG4 Comparators LCD Driver © 2009 Microchip Technology Inc. ...
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... RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 2.0 “Oscillator Configurations” for more information. 3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Data Bus<8> Data Latch ...
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... I/O TTL Digital I/O. I Analog Analog input 4. O Analog SEG15 output for LCD. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2009 Microchip Technology Inc. ...
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... P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... SEG27 output for LCD. I/O ST Digital I/ EUSART asynchronous receive. I/O ST EUSART synchronous data (see related TX1/CK1). O Analog SEG28 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description 2 C™ mode © 2009 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O ...
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... I/O ST Digital I/O. O Analog COM3 output for LCD. I/O ST Digital I/O. I/O ST Capture 2 input/Compare 2 output/PWM2 output. O Analog SEG31 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2009 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O ...
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... Core logic power or external filter capacitor connection. P — Positive supply for microcontroller core logic (regulator disabled). P — External filter capacitor connection (regulator enabled). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2009 Microchip Technology Inc. ...
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... I = Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Pin Buffer Type Type I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2009 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... Analog SEG5 output for LCD. I/O ST Digital I/O. O Analog SEG6 output for LCD. I/O ST Digital I/O. O Analog SEG7 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2009 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O ...
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... SEG24 output for LCD. I Analog Comparator 1 input A. I/O ST Digital I/O. O Analog Analog input 5. I TTL SPI slave select input. O Analog SEG25 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2009 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... Analog SEG41 output for LCD. I/O ST Digital I/O. O Analog SEG42 output for LCD. I/O ST Digital I/O. O Analog SEG43 output for LCD. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2009 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Pin Buffer Type Type PORTJ is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F87J90 FAMILY NOTES: DS39933C-page 28 Preliminary © 2009 Microchip Technology Inc. ...
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... MHz Source (INTOSC) INTRC Source 31 kHz (INTRC) © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY All of these modes are selected by the user by programming the FOSC<2:0> Configuration bits. In addition, PIC18F87J90 family devices can switch between different clock sources, either under software control or automatically under certain conditions. This ...
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... Phase Locked Loop (PLL) (see Section 2.4.3 “PLL Frequency Multiplier”). (2) R/W-0 R (3) (3) IRCF0 OSTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (3) (4) (2) (5) Preliminary (1) R-0 R/W-0 R/W-0 (5) (5) IOFS SCS1 SCS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F87J90 family devices offer the Timer1 oscillator as a secondary oscillator source. This oscillator, in all power-managed modes, is often the time base for © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY R/W-0 R/W-0 R/W-0 ...
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... This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”. Preliminary © 2009 Microchip Technology Inc. ...
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... AN943, “Practical PIC Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” See the notes following Table 2-2 for additional information. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Osc Type Freq ...
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... In this configuration, the PLL is enabled in software and generates a clock output MHz. The operation of INTOSC with the PLL is described in Section 2.5.2 “INTPLL Modes”. Preliminary © 2009 Microchip Technology Inc. the PLLEN bit Phase Comparator ...
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... OSC1 functions as RA7 (see Figure 2-6) for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6 (see Figure 2-7), both for digital input and output. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY FIGURE 2-6: RA7 F ...
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... To compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE register. Preliminary © 2009 Microchip Technology Inc. ...
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... I/O pin RA6, direction controlled by TRISA<6> Note: See Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Timer1 oscillator may be operating to support a Real- Time Clock (RTC). Other features may be operating that do not require a device clock source (i.e., MSSP slave, INTx pins and others) ...
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... PIC18F87J90 FAMILY NOTES: DS39933C-page 38 Preliminary © 2009 Microchip Technology Inc. ...
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... RC_IDLE 1 11 Note 1: IDLEN reflects its value when the SLEEP instruction is executed. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 3.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • the primary clock, as defined by the FOSC<2:0> ...
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... SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situa- tions, initial oscillator operation is far from stable and unpredictable operation may result. Preliminary © 2009 Microchip Technology Inc. ...
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... These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition PLL ( n-1 n Clock Transition PC OSTS bit Set = 2 ms (approx). These intervals are not shown to scale. Preliminary © 2009 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD PC Preliminary © 2009 Microchip Technology Inc. ...
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... Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F87J90 FAMILY NOTES: DS39933C-page 46 Preliminary © 2009 Microchip Technology Inc. ...
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... Ripple Counter Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1 ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39933C-page 48 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises to the point where DD regulator output is sufficient, the Power-up Timer will execute the additional time delay. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY FIGURE 4- ...
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... PWRT will expire. Bringing MCLR high will begin (Figure 4-5). This is useful for testing purposes synchronize more than one PIC18FXXXX device operating in parallel. T PWRT T PWRT Preliminary © 2009 Microchip Technology Inc. all depict time-out execution immediately , V RISE < PWRT ): CASE 1 ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY T PWRT , V RISE > 3. PWRT Preliminary ): CASE 2 DD ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register ( 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Preliminary STKPTR Register POR BOR STKFUL STKUNF © 2009 Microchip Technology Inc. ...
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... See Table 4-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY MCLR Resets Power-on Reset, ...
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... Preliminary © 2009 Microchip Technology Inc. Wake-up via WDT or Interrupt ---- uuuu uuuu uuuu ---- uuuu N/A N/A N/A N/A N/A ---- uuuu ...
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... See Table 4-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY MCLR Resets Power-on Reset, ...
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... Preliminary © 2009 Microchip Technology Inc. Wake-up via WDT or Interrupt -uuu 1111 (3) -uuu 0000 -uuu 0000 uu-- uuu- (3) uu-- uuu- uu-- uuu- -uuu u-uu ...
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... See Table 4-1 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY MCLR Resets Power-on Reset, ...
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... Preliminary © 2009 Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu u-uu uuuu ...
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... Config. Words Unimplemented Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space ...
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... Additional details on the device Configuration Words are provided in Section 24.1 “Configuration Bits”. TABLE 5-1: FLASH CONFIGURATION WORD FOR PIC18F87J90 FAMILY DEVICES Program Device Memory (Kbytes) PIC18F66J90 64 PIC18F86J90 PIC18F67J90 128 PIC18F87J90 Preliminary © 2009 Microchip Technology Inc. CONFIG1 through Configuration Word Addresses FFF8h to FFFFh 1FFF8h to 1FFFFh ...
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... TOSH TOSL 00h 1Ah 34h © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary and POP Instructions R/W-0 R/W-0 SP1 SP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 5.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Fetch INST ( Execute INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Preliminary Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 © 2009 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Preliminary © 2009 Microchip Technology Inc. ...
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... Note 1: Addresses F5Ah through F5Fh also are used by SFRs, but are not part of the Access RAM. Users must always use the complete address – or load the proper SBR value – to access these registers. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY When ...
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... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Preliminary (2) From Opcode © 2009 Microchip Technology Inc. ...
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... Unimplemented registers are read as ‘0’. 3: This register is not available on PIC18F6XJ90 devices. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions ...
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... N/A 53, 78 N/A 53, 78 54, 77 ---- xxxx 54, 77 xxxx xxxx 54, 66 ---- 0000 N/A 54, 77 N/A 54, 78 N/A 54, 78 N/A 54, 78 N/A 54, 78 54, 77 ---- xxxx 54, 77 xxxx xxxx DC C 54, 75 ---x xxxx C™ Slave mode. See Section 17.4.3.2 “Address © 2009 Microchip Technology Inc. ...
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... RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY ...
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... LATE1 LATE0 56, 123 xxxx x-xx LATD1 LATD0 56, 121 xxxx xxxx LATC1 LATC0 56, 119 xxxx xxxx LATB1 LATB0 56, 116 xxxx xxxx LATA1 LATA0 56, 113 xxxx xxxx C™ Slave mode. See Section 17.4.3.2 “Address © 2009 Microchip Technology Inc. ...
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... RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY ...
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... ALRMPTR1 ALRMPTR0 0000 0000 58, 153 ARPT1 ARPT0 58, 154 0000 0000 58, 157 xxxx xxxx 58, 157 xxxx xxxx IDISSEN CTTRIG 58, 315 0-00 0000 58, 316 IRNG1 IRNG0 58, 317 0000 0000 — 58, 152 ---- -00- C™ Slave mode. See Section 17.4.3.2 “Address © 2009 Microchip Technology Inc. ...
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... For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY register then reads back as ‘000u u1uu’ recom- ...
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... HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 BTFSS FSR0H, 1 BRA NEXT CONTINUE Preliminary © 2009 Microchip Technology Inc. other Stack Pointer ; Clear INDF ; register then ; inc pointer ; All done with ; Bank1? ; NO, clear next ; YES, continue ...
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... FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
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... Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 5.2.4 “Two-Word Instructions”. Preliminary © 2009 Microchip Technology Inc. ...
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... Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 5.6.2 INSTRUCTIONS AFFECTED BY ...
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... F00h Bank 15 F40h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 060h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F40h SFRs FFFh Data Memory Preliminary © 2009 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... F00h BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or ...
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... PIC18F87J90 FAMILY NOTES: DS39933C-page 82 Preliminary © 2009 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Reset write operation was Reading attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Preliminary Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
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... Write cycle is complete bit 0 Unimplemented: Read as ‘0’ Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY R/W-0 R/W-x R/W-0 (1) FREE ...
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... Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ: TBLPTR<21:0> Preliminary TBLPTRL 0 © 2009 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 90
... The CPU will stall for duration of the erase for T (see parameter D133B Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary © 2009 Microchip Technology Inc. ...
Page 91
... Write the 64 bytes into the holding registers with auto-increment. 7. Set the WREN bit (EECON1<2>) to enable byte writes. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
Page 92
... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block Preliminary © 2009 Microchip Technology Inc. ...
Page 93
... Sequence MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WPROG BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 3. Set WPROG to enable single-word write. 4. Set WREN to enable write to memory. 5. Disable interrupts. 6. Write 55h to EECON2. 7. Write 0AAh to EECON2. 8. ...
Page 94
... Protection” for details on code protection of Flash program memory. Bit 5 Bit 4 Bit 3 Bit 2 bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) INT0IE RBIE TMR0IF FREE WRERR WREN Preliminary Reset Bit 1 Bit 0 Values on Page INT0IF RBIF — 55 © 2009 Microchip Technology Inc. ...
Page 95
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY EXAMPLE 7- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
Page 96
... RES2 WREG ; RES3 ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products RES2 WREG ; RES3 ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H RES3 ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H RES3 © 2009 Microchip Technology Inc. ...
Page 97
... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 98
... PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Preliminary © 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 99
... None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Note: Interrupt flag bits are set when an interrupt ...
Page 100
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39933C-page 98 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 101
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY R/W-0 ...
Page 102
... R-0 R/W-0 U-0 TX1IF SSPIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 103
... The device voltage is above the regulator’s low-voltage trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY U-0 R/W-0 R/W-0 — BCLIF LVDIF U = Unimplemented bit, read as ‘ ...
Page 104
... RTCCIF: RTCC Interrupt Flag bit 1 = RTCC interrupt occured (must be cleared in software RTCC interrupt occured DS39933C-page 102 R-0 R/W-0 R/W-0 TX2IF CTMUIF CCP2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CCP1IF RTCCIF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 105
... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY R/W-0 R/W-0 U-0 TX1IE SSPIE — ...
Page 106
... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘0’ DS39933C-page 104 U-0 R/W-0 R/W-0 — BCLIE LVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 U-0 TMR3IE — bit Bit is unknown ...
Page 107
... Disabled bit 1 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 0 RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY R-0 R/W-0 R/W-0 TX2IE CTMUIE CCP2IE U = Unimplemented bit, read as ‘0’ ...
Page 108
... TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39933C-page 106 R/W-1 R/W-1 U-0 TX1IP SSPIP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 109
... LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY U-0 R/W-1 R/W-1 — BCLIP LVDIP U = Unimplemented bit, read as ‘0’ ...
Page 110
... Low priority bit 0 RTCCIP: RTCC Interrupt Priority bit 1 = High priority 0 = Low priority DS39933C-page 108 R-1 R/W-1 R/W-1 TX2IP CTMUIP CCP2IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 CCP1IP RTCCIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 111
... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...
Page 112
... Example 8-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary © 2009 Microchip Technology Inc. ...
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... TRIS Latch RD TRIS PORT © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 9.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 9 ...
Page 114
... ADCON1 ; for digital inputs MOVLW 0BFh MOVWF TRISA 5V Preliminary and OSC1/CLKI/RA7 normally INITIALIZING PORTA ; Initialize PORTA by ; clearing output latches ; Alternate method to ; clear output data latches ; Configure A/D ; Value used to initialize ; data direction ; Set RA<7, 5:0> as inputs, ; RA<6> as output © 2009 Microchip Technology Inc. ...
Page 115
... Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘x’. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY I/O I/O ...
Page 116
... RB<3:2> are multiplexed as CTMU edge inputs. RB<5:0> also are multiplexed with LCD segment drives, controlled by bits in the LCDSE1 and LCDSE3 registers. I/O port functionality is only available when the LCD segments are disabled. Preliminary © 2009 Microchip Technology Inc. wake the device from ...
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... Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY I/O I/O ...
Page 118
... INTEDG3 TMR0IP INT3IE INT2IE INT1IE INT3IF SE13 SE12 SE11 SE10 SE29 SE28 SE27 SE26 Preliminary Reset Bit 1 Bit 0 Values on page RB1 RB0 57 LATB1 LATB0 56 TRISB1 TRISB0 56 INT0IF RBIF 53 INT3IP RBIP 53 INT2IF INT1IF 53 SE09 SE08 55 SE25 SE24 55 © 2009 Microchip Technology Inc. ...
Page 119
... TRIS bit settings. Note: These pins are configured as digital inputs on any device Reset. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. RC< ...
Page 120
... Asynchronous serial receive data input (EUSART module). DIG Synchronous serial data output (EUSART module); takes priority over port data. ST Synchronous serial data input (EUSART module); user must configure as an input. ANA LCD segment 28 output; disables all other pin functions. Preliminary © 2009 Microchip Technology Inc. ...
Page 121
... SE23 SE22 LCDSE3 SE31 SE30 (1) (1) LCDSE4 SE39 SE38 Legend: Shaded cells are not used by PORTC. Note 1: Unimplemented on PIC18F6XJ90 devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATCB4 LATC3 ...
Page 122
... EXAMPLE 9-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Preliminary © 2009 Microchip Technology Inc. ...
Page 123
... TRISD TRISD7 TRISD6 PORTG RDPU REPU LCDSE0 SE07 SE06 Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on PIC18F6XJ90 devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY I/O I/O Type O DIG LATD<0> data output PORTD<0> data input. O ANA LCD segment 0 output ...
Page 124
... MOVWF TRISE for I/O RE6 None Preliminary parts has the function of INITIALIZING PORTE ; Initialize PORTE by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RE<1:0> as inputs ; RE<7:2> as outputs © 2009 Microchip Technology Inc. ...
Page 125
... TRISG SPIOD CCP2OD CCP1OD LCDCON LCDEN SLPEN LCDSE3 SE31 SE30 Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on PIC18F6XJ90 devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY I/O I/O Type O DIG LATE<0> data output PORTE<0> data input. I ANA LCD module bias voltage input ...
Page 126
... MOVLW 07h ; MOVWF CMCON ; Turn off comparators MOVLW 0Fh ; MOVWF ADCON1 ; Set PORTF as digital I/O MOVLW 0CEh ; Value used to ; initialize data ; direction MOVWF TRISF ; Set RF3:RF1 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs Preliminary © 2009 Microchip Technology Inc. ...
Page 127
... Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY I/O I/O ...
Page 128
... CIS CM2 CVRR CVRSS CVR3 CVR2 SE21 SE20 SE19 SE18 SE29 SE28 SE27 SE26 Preliminary Reset Bit 1 Bit 0 Values on page RF1 — 56 LATF1 — 56 TRISF1 — 56 PCFG1 PCFG0 55 CM1 CM0 55 CVR1 CVR0 55 SE17 SE16 55 SE25 SE24 55 © 2009 Microchip Technology Inc. ...
Page 129
... The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Although the port itself is only five bits wide, the PORTG<7:5> bits are still implemented to control the weak pull-ups on the I/O ports associated with PORTD, PORTE and PORTJ ...
Page 130
... RTCC output. Bit 5 Bit 4 Bit 3 Bit 2 (1) RJPU RG4 RG3 RG2 — LATG4 LATG3 LATG2 TRISG3 TRISG2 SE29 SE28 SE27 SE26 Preliminary Description Reset Bit 1 Bit 0 Values on page RG1 RG0 56 LATG1 LATG0 56 TRISG1 TRISG0 56 SE25 SE24 55 © 2009 Microchip Technology Inc. ...
Page 131
... All PORTH pins are multiplexed with LCD segment drives controlled by the LCDSE5 register. I/O port functions are only available when the segments are disabled. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY EXAMPLE 9-8: INITIALIZING PORTH CLRF PORTH ...
Page 132
... LCD segment 43 output; disables all other pin functions. Bit 5 Bit 4 Bit 3 Bit 2 RH5 RH4 RH3 RH2 LATH5 LATH4 LATH3 LATH2 TRISH5 TRISH4 TRISH3 TRISH2 SE45 SE44 SE43 SE42 Preliminary Description Reset Bit 1 Bit 0 Values on page RH1 RH0 56 LATH1 LATH0 56 TRISH1 TRISH0 56 SE41 SE40 55 © 2009 Microchip Technology Inc. ...
Page 133
... LCDSE4 register. I/O port functions are only available on these pins when the segments are disabled. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Each of the PORTJ pins has a weak internal pull-up. The pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up ...
Page 134
... RJ5 RJ4 RJ3 RJ2 LATJ5 LATJ4 LATJ3 LATJ2 TRISJ5 TRISJ4 TRISJ3 TRISJ2 (1) RG4 RG3 RG2 SE37 SE36 SE35 SE34 Preliminary Description Reset Bit 1 Bit 0 Values on page RJ1 RJ0 56 LATJ1 LATJ0 56 TRISJ1 TRISJ0 56 RG1 RG0 56 SE33 SE32 55 © 2009 Microchip Technology Inc. ...
Page 135
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 10-1 ...
Page 136
... Sync with Internal TMR0L Clocks Delay Preliminary ). There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 137
... RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 10.3.1 ...
Page 138
... PIC18F87J90 FAMILY NOTES: DS39933C-page 136 Preliminary © 2009 Microchip Technology Inc. ...
Page 139
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 140
... Special Event Trigger) Preliminary 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 141
... PIC18F87J90 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 11-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY TABLE 11-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Oscillator Freq. Type LP 32.768 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 142
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary © 2009 Microchip Technology Inc. ...
Page 143
... Timer1 Register High Byte T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 144
... PIC18F87J90 FAMILY NOTES: DS39933C-page 142 Preliminary © 2009 Microchip Technology Inc. ...
Page 145
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 12.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 146
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSPIF TX1IE SSPIE TX1IP SSPIP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 53 — TMR2IF TMR1IF 56 — TMR2IE TMR1IE 56 — TMR2IP TMR1IP © 2009 Microchip Technology Inc. ...
Page 147
... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The Timer3 module is controlled through the T3CON register (Register 13-1) ...
Page 148
... RC1/T1OSI and 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 149
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 13.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 150
... PIC18F87J90 FAMILY NOTES: DS39933C-page 148 Preliminary © 2009 Microchip Technology Inc. ...
Page 151
... Input from Timer1 Oscillator Internal RC Alarm Event © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY The RTCC module is intended for applications, where accurate time must be maintained for extended period with minimum to no intervention from the CPU. The module is optimized for low-power usage in order to provide extended battery life while keeping track of time ...
Page 152
... Alarm Value Registers • ALRMVALH and ALRMVALL – Can access the following registers: - ALRMMNTH - ALRMDAY - ALRMWD - ALRMHR - ALRMMIN - ALRMSEC Note: The RTCVALH and RTCVALL registers can be accessed through RTCRPT<1:0>. ALRMVALH and ALRMVALL can be accessed through ALRMPTR<1:0>. Preliminary © 2009 Microchip Technology Inc. ...
Page 153
... The RTCCFG register is only affected by a POR. For resets other than POR, RTCC will continue to run even if the device is in Reset write to the RTCEN bit is only allowed when RTCWREN = 1. 3: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY (1) R-0 R-0 R/W-0 ...
Page 154
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 R/W-0 (1) — — RTSECSEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 CAL1 CAL0 bit Bit is unknown R/W-0 U-0 (1) RTSECSEL0 — bit Bit is unknown (2) , © 2009 Microchip Technology Inc. ...
Page 155
... The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVALH ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVALL ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY R/W-0 R/W-0 R/W-0 AMASK2 AMASK1 AMASK0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared th , once every four years) ...
Page 156
... R/W-x R/W-x YRTEN0 YRONE3 YRONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 ARPT1 ARPT0 bit Bit is unknown U-0 U-0 — — bit Bit is unknown R/W-x R/W-x YRONE1 YRONE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 157
... Bit is set bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit Contains a value from Note 1: A write to this register is only allowed when RTCWREN = 1. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY (1) R/W-x R/W-x R/W-x MTHTEN0 MTHONE3 MTHONE2 U = Unimplemented bit, read as ‘ ...
Page 158
... R/W-x R/W-x SECTEN0 SECONE3 SECONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-x R/W-x HRONE1 HRONE0 bit Bit is unknown R/W-x R/W-x MINONE1 MINONE0 bit Bit is unknown R/W-x R/W-x SECONE1 SECONE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 159
... Bit is set bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit Contains a value from Note 1: A write to this register is only allowed when RTCWREN = 1. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY (1) R/W-x R/W-x R/W-x MTHTEN0 MTHONE3 MTHONE2 U = Unimplemented bit, read as ‘ ...
Page 160
... R/W-x R/W-x SECTEN0 SECONE3 SECONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-x R/W-x HRONE1 HRONE0 bit Bit is unknown R/W-x R/W-x MINONE1 MINONE0 bit Bit is unknown R/W-x R/W-x SECONE1 SECONE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 161
... FIGURE 14-3: ALARM DIGIT FORMAT Hours (24-hour format) 0-2 0-9 © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 14.2 Operation 14.2.1 REGISTER INTERFACE The register interface for the RTCC and alarm values is implemented using the Binary Coded Decimal (BCD) format. This simplifies the firmware, when using the module, as each of the digits is contained within its own 4-bit value (see Figure 14-2 and Figure 14-3) ...
Page 162
... Note 1: See Section 14.2.4 “Leap Year”. Preliminary One Second clock (1) Month Year DAY OF WEEK SCHEDULE Day of Week DAY TO MONTH ROLLOVER SCHEDULE Maximum Day Field 31 ( © 2009 Microchip Technology Inc. ...
Page 163
... This firmware solution would consist of reading each register twice and then comparing the two values. If the two values matched, then a rollover did not occur. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 14.2.7 WRITE LOCK In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RTCCFG< ...
Page 164
... To avoid this, only change the timer and alarm values while the alarm is disabled (ALRMEN = 0 recom- mended ALRMRPT registers and CHIME bit be changed when RTCSYNC = 0. Preliminary that the ALRMCFG and © 2009 Microchip Technology Inc. ...
Page 165
... Indefinite repetition of the alarm can occur if the CHIME bit = 1. When CHIME = 1, the alarm is not disabled when the ALRMRPT register reaches ‘00’, but it rolls over to FF and continues counting indefinitely. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Day of the Week Month ...
Page 166
... POR. Once the device exits the POR state, the clock registers should be reloaded with the desired values. The timer prescaler values can be reset only by writing to the SECONDS register. No device Reset can affect the prescalers. Preliminary © 2009 Microchip Technology Inc. ...
Page 167
... ALRMVALH Alarm Value High Register Window Based on ALRMPTR<1:0> ALRMVALL Alarm Value Low Register Window Based on ALRMPTR<1:0> Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 80-pin devices. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 168
... PIC18F87J90 FAMILY NOTES: DS39933C-page 166 Preliminary © 2009 Microchip Technology Inc. ...
Page 169
... PWM mode Note 1: CCPxM<3:0> = 1011 will only reset timer and not start A/D conversion on CCP1 match. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Each CCP module contains two 8-bit registers that can operate as two 8-bit Capture registers, two 8-bit Compare registers or two PWM Master/Slave Duty Cycle registers ...
Page 170
... TMR1 TMR3 CCP1 CCP2 TMR2 Timer3 is used for all capture and compare operations for all CCP modules. Timer2 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. © 2009 Microchip Technology Inc. ...
Page 171
... Capture PWM None Compare PWM None PWM Capture None PWM Compare None PWM PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Interaction Preliminary DS39933C-page 169 ...
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... CAPTURE PRESCALERS ; Turn CCP module off ; new prescaler mode ; value and CCP ON ; Load CCP2CON with ; this value TMR3H TMR3L TMR3 Enable CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L TMR3 Enable CCPR2H CCPR2L TMR1 Enable TMR1H TMR1L © 2009 Microchip Technology Inc. ...
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... TMR3H TMR3L T3CCP1 Comparator CCPR2H CCPR2L © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 15.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP2M<3:0> = 1010), the CCP2 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP2IE bit is set. ...
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... CCP2M2 CCP2M1 CCP2M0 Preliminary Reset Bit 1 Bit 0 Values on Page INT0IF RBIF 53 PD POR BOR 54 CCP1IF RTCCIF 56 CCP1IE RTCCIE 56 CCP1IP RTCCIP 56 TMR3IF — 56 TMR3IE — 56 TMR3IP — 56 TRISC1 TRISC0 56 — TRISE1 TRISE0 56 TRISG1 TRISG0 TMR1CS TMR1ON TMR3CS TMR3ON © 2009 Microchip Technology Inc. ...
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... The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY A PWM output (Figure 15-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
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... PWM period, the CCP2 pin will not be cleared. 9.77 kHz 39.06 kHz FFh FFh Preliminary F ⎛ ⎞ OSC log --------------- ⎝ ⎠ F PWM = -----------------------------bits log 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2009 Microchip Technology Inc. ...
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... CCPR2H Capture/Compare/PWM Register 2 High Byte CCP2CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 3. Make the CCP2 pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON ...
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... PIC18F87J90 FAMILY NOTES: DS39933C-page 176 Preliminary © 2009 Microchip Technology Inc. ...
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... LCD Clock T13CKI Source Select INTRC Oscillator INTOSC Oscillator © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY The LCD driver module supports these features: • Direct driving of LCD panel • On-chip bias generator with dedicated charge pump to support a range of fixed and variable bias options • ...
Page 180
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) Maximum Number of Pixels: PIC18F6XJ90 PIC18F8XJ90 132 Preliminary register, shown in Register 16-2, (LCDSE5:LCDSE0), listed in R/W-0 R/W-0 LMUX1 LMUX0 bit Bit is unknown Bias Type 48 Static 96 1/2 or 1/3 144 1/2 or 1/3 192 1/3 © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F87J90 FAMILY R-0 R/W-0 R/W-0 WA LP3 LP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... LCDSE4<7:1> (SEG<39:33>) are not implemented in PIC18F6XJ90 devices. 2: LCDSE5 is not implemented in PIC18F6XJ90 devices. DS39933C-page 180 R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Segments Preliminary R/W-0 R/W-0 SE SE(n) bit Bit is unknown 7:0 15:8 23:16 31:24 39:32 47:40 © 2009 Microchip Technology Inc. ...
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... Bits<7:1> of these registers are not implemented in PIC18F6XJ90 devices. Bit 0 of these registers (SEG32Cy) is always implemented. 2: These registers are not implemented on PIC18F6XJ90 devices. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY Individual LCDDATA bits are named by the convention “SxxCy”, with “xx” as the segment number and “y” as the common number ...
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... LCD clock source or for any other purpose, LCD segment 32 become unavailable. LCDPS<3:0> 4 ÷4 00 ÷2 01 1:1 to 1:16 Programmable Prescaler ÷256 10 01 Preliminary /4 frequency of 8 MHz). OSC /4 clock OSC COM0 ÷32 ÷ COM1 or COM2 Ring Counter ÷8192 COM3 31 kHz Clock to LCD Charge Pump © 2009 Microchip Technology Inc. ...
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... CKSEL<1:0>: Regulator Clock Source Select bits 11 = INTRC 10 = INTOSC 8 MHz source 01 = Timer1 oscillator 00 = LCD regulator disabled © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 16.3.2 LCD VOLTAGE REGULATOR The purpose of the LCD regulator is to provide proper bias voltage and good contrast for the LCD, regardless of V levels ...
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... M1 (Regulator without Boost the voltage BIAS for the application is expected to DD (Figure 16-3 with M0, changing BIAS will also change; where in BIAS is constant. BIAS FLY 0.47 μF ( 0.47 μF (1) C1 0.47 μF (1) C0 0.47 μF (1) Mode 1 ≤ BIAS DD © 2009 Microchip Technology Inc. ...
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... LCDBIAS3 Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer based on the actual LCD specifications. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY configuration of the resistor ladder. Most applications using M2 will use a 1/3 or 1/2 Bias type. While Static ...
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... M3 is selected by clearing the CKSEL<1:0> and CPEN bits (2) 10 kΩ 10 kΩ Static Bias 1/2 Bias Bias Type Static 1/2 Bias 1 1 Preliminary (1) (1) 10 kΩ (1) 10 kΩ (1) (1) 10 kΩ 1/3 Bias 1/3 Bias © 2009 Microchip Technology Inc. ...
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... LCDBIAS pins can be changed to increase or decrease current. As always, any changes should be evaluated in the actual circuit for its impact on the application. © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY 16.4 LCD Multiplex Types The LCD driver module can be configured into four multiplex types: • ...
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... Thus, always take care to see that the V on all pixels is ‘0’ whenever Sleep mode is invoked. Figure 16-6 through Figure 16-16 provide waveforms for static, half multiplex, one-third multiplex and quarter multiplex drives for Type-A and Type-B waveforms. Preliminary on all the pixels DC DC © 2009 Microchip Technology Inc. ...
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... FIGURE 16-6: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE COM0 © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY COM0 SEG0 SEG1 COM0-SEG0 COM0-SEG1 1 Frame Preliminary DS39933C-page 189 ...
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... PIC18F87J90 FAMILY FIGURE 16-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS39933C-page 190 COM0 COM1 SEG0 SEG1 1 Frame Preliminary © 2009 Microchip Technology Inc. ...
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... FIGURE 16-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY COM0 COM1 SEG0 SEG1 2 Frames Preliminary DS39933C-page 191 ...
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... PIC18F87J90 FAMILY FIGURE 16-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS39933C-page 192 COM0 COM1 SEG0 SEG1 1 Frame Preliminary © 2009 Microchip Technology Inc. ...
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... FIGURE 16-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY COM0 COM1 SEG0 SEG1 2 Frames Preliminary DS39933C-page 193 ...
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... PIC18F87J90 FAMILY FIGURE 16-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS39933C-page 194 COM0 COM1 COM2 SEG0 SEG2 SEG1 Preliminary Frame © 2009 Microchip Technology Inc. ...
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... FIGURE 16-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY COM0 COM1 COM2 SEG0 SEG1 Preliminary Frames DS39933C-page 195 ...
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... PIC18F87J90 FAMILY FIGURE 16-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 DS39933C-page 196 COM0 COM1 COM2 SEG0 SEG2 SEG1 COM0-SEG0 COM0-SEG1 Preliminary Frame © 2009 Microchip Technology Inc. ...
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... FIGURE 16-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2009 Microchip Technology Inc. PIC18F87J90 FAMILY COM0 COM1 COM2 SEG0 SEG1 Preliminary Frames DS39933C-page 197 ...
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... PIC18F87J90 FAMILY FIGURE 16-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS39933C-page 198 COM0 COM1 COM2 COM3 SEG0 SEG1 1 Frame Preliminary © 2009 Microchip Technology Inc. ...