PIC18F67J90-I/PT Microchip Technology, PIC18F67J90-I/PT Datasheet - Page 439

• Manufacturer Part Number: PIC18F67J90-I/PT
• Description: IC PIC MCU FLASH 128KB 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 3.8310546875KB
• Cpu Speed: 48MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

SS ..................................................................................... 205
SSPOV.............................................................................. 239
SSPOV Status Flag .......................................................... 239
SSPSTAT Register
Stack Full/Underflow Resets ............................................... 63
SUBFSR ........................................................................... 379
SUBFWB........................................................................... 368
SUBLW ............................................................................. 369
SUBULNK ......................................................................... 379
SUBWF ............................................................................. 369
SUBWFB........................................................................... 370
SWAPF ............................................................................. 370
T
Table Pointer Operations (table) ......................................... 86
Table Reads/Table Writes .................................................. 63
TBLRD .............................................................................. 371
TBLWT .............................................................................. 372
Timer0 ............................................................................... 133
Timer1 ............................................................................... 137
Timer2 ............................................................................... 143
© 2009 Microchip Technology Inc.
Associated Registers ................................................ 213
Bus Mode Compatibility ............................................ 213
Effects of a Reset...................................................... 213
Enabling SPI I/O ....................................................... 209
Master Mode ............................................................. 210
Operation .................................................................. 208
Operation in Power-Managed Modes ....................... 213
Serial Clock............................................................... 205
Serial Data In ............................................................ 205
Serial Data Out ......................................................... 205
Slave Mode ............................................................... 211
Slave Select .............................................................. 205
Slave Select Synchronization ................................... 211
SPI Clock .................................................................. 210
Typical Connection ................................................... 209
R/W Bit.............................................................. 219, 221
Associated Registers ................................................ 135
Clock Source Select (T0CS Bit)................................ 134
Operation .................................................................. 134
Overflow Interrupt ..................................................... 135
Prescaler................................................................... 135
Prescaler Assignment (PSA Bit) ............................... 135
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 135
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................. 134
Source Edge Select (T0SE Bit)................................. 134
16-Bit Read/Write Mode............................................ 139
Associated Registers ................................................ 141
Interrupt..................................................................... 140
Operation .................................................................. 138
Oscillator ........................................................... 137, 139
Oscillator, as Secondary Clock ................................... 31
Overflow Interrupt ..................................................... 137
Resetting, Using the CCP Special Event Trigger...... 140
TMR1H Register ....................................................... 137
TMR1L Register........................................................ 137
Use as a Clock Source ............................................. 139
Use as a Real-Time Clock ........................................ 140
Associated Registers ................................................ 144
Interrupt..................................................................... 144
Operation .................................................................. 143
Output ....................................................................... 144
PR2 Register............................................................. 173
Switching Assignment....................................... 135
Layout Considerations ...................................... 140
Preliminary
PIC18F87J90 FAMILY
Timer3 .............................................................................. 145
Timing Diagrams
TMR2 to PR2 Match Interrupt................................... 173
16-Bit Read/Write Mode ........................................... 147
Associated Registers................................................ 147
Operation.................................................................. 146
Oscillator........................................................... 145, 147
Overflow Interrupt ............................................. 145, 147
Special Event Trigger (CCP) .................................... 147
TMR3H Register....................................................... 145
TMR3L Register ....................................................... 145
A/D Conversion ........................................................ 420
Acknowledge Sequence ........................................... 242
Asynchronous Reception.................................. 261, 277
Asynchronous Transmission ............................ 259, 275
Asynchronous Transmission (Back to Back) .... 259, 275
Automatic Baud Rate Calculation............................. 257
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep.................... 262
Baud Rate Generator with Clock Arbitration............. 236
BRG Overflow Sequence ......................................... 257
BRG Reset Due to SDA Arbitration During
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition (SCL = 0) ..... 245
Bus Collision During a Stop Condition (Case 1)....... 247
Bus Collision During a Stop Condition (Case 2)....... 247
Bus Collision During Start Condition (SDA Only) ..... 244
Bus Collision for Transmit and Acknowledge ........... 243
Capture/Compare/PWM ........................................... 409
CLKO and I/O ........................................................... 406
Clock Synchronization .............................................. 229
Clock/Instruction Cycle ............................................... 64
EUSART/AUSART Synchronous
EUSART/AUSART Synchronous
Example SPI Master Mode (CKE = 0) ...................... 410
Example SPI Master Mode (CKE = 1) ...................... 411
Example SPI Slave Mode (CKE = 0) ........................ 412
Example SPI Slave Mode (CKE = 1) ........................ 413
External Clock .......................................................... 404
Fail-Safe Clock Monitor ............................................ 331
First Start Bit Timing ................................................. 237
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C Bus Data............................................................. 415
C Bus Start/Stop Bits ............................................. 414
C Master Mode (7 or 10-Bit Transmission) ............ 240
C Master Mode (7-Bit Reception) .......................... 241
C Slave Mode (10-Bit Reception,
C Slave Mode (10-Bit Reception, SEN = 0) ........... 225
C Slave Mode (10-Bit Reception, SEN = 1) ........... 231
C Slave Mode (10-Bit Transmission) ..................... 227
C Slave Mode (7-Bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............. 222
C Slave Mode (7-Bit Reception, SEN = 1) ............. 230
C Slave Mode (7-Bit Transmission) ....................... 224
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode......... 242
Normal Operation ............................................. 262
Start Condition.................................................. 245
Condition (Case 1)............................................ 246
Condition (Case 2)............................................ 246
Receive (Master/Slave) .................................... 418
Transmission (Master/Slave)............................ 418
SEN = 0, ADMSK = 01001) .............................. 226
ADMSK = 01011) ............................................. 223
Sequence (7 or 10-Bit Addressing Mode) ........ 232
DS39933C-page 437