PIC18F67J90-I/PT Microchip Technology, PIC18F67J90-I/PT Datasheet - Page 440

• Manufacturer Part Number: PIC18F67J90-I/PT
• Description: IC PIC MCU FLASH 128KB 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 3.8310546875KB
• Cpu Speed: 48MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J90 FAMILY
Timing Diagrams and Specifications
DS39933C-page 438
LCD Interrupt in Quarter Duty Cycle Drive................ 200
LCD Sleep Entry/Exit When SLPEN = 1
MSSP I
MSSP I
PWM Output ............................................................. 173
Repeated Start Condition.......................................... 238
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................. 263
Slave Synchronization .............................................. 211
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) .......................................... 210
SPI Mode (Slave Mode, CKE = 0) ............................ 212
SPI Mode (Slave Mode, CKE = 1) ............................ 212
Synchronous Reception
Synchronous Transmission............................... 264, 278
Synchronous Transmission (Through TXEN) ... 265, 279
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Timer Pulse Generation ............................................ 164
Timer0 and Timer1 External Clock ........................... 408
Transition for Entry to Idle Mode ................................. 44
Transition for Entry to SEC_RUN Mode ..................... 41
Transition for Entry to Sleep Mode ............................. 43
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode ............... 44
Transition for Wake From Sleep (HSPLL) .................. 43
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
Transition to RC_RUN Mode ...................................... 42
Type-A in 1/2 MUX, 1/2 Bias Drive ........................... 190
Type-A in 1/2 MUX, 1/3 Bias Drive ........................... 192
Type-A in 1/3 MUX, 1/2 Bias Drive ........................... 194
Type-A in 1/3 MUX, 1/3 Bias Drive ........................... 196
Type-A in 1/4 MUX, 1/3 Bias Drive ........................... 198
Type-A/Type-B in Static Drive................................... 189
Type-B in 1/2 MUX, 1/2 Bias Drive ........................... 191
Type-B in 1/2 MUX, 1/3 Bias Drive ........................... 193
Type-B in 1/3 MUX, 1/2 Bias Drive ........................... 195
Type-B in 1/3 MUX, 1/3 Bias Drive ........................... 197
Type-B in 1/4 MUX, 1/3 Bias Drive ........................... 199
Capture/Compare/PWM Requirements .................... 409
CLKO and I/O Requirements .................................... 406
EUSART/AUSART Synchronous Receive
EUSART/AUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
or CS1:CS0 = 00............................................... 201
Timer (OST) and Power-up Timer (PWRT) ...... 407
V
(Master Mode, SREN)............................... 266, 280
Not Tied to V
Not Tied to V
Tied to V
(INTRC to HSPLL) ............................................ 329
PRI_RUN Mode .................................................. 42
PRI_RUN Mode (HSPLL) ................................... 41
Requirements.................................................... 418
Requirements.................................................... 418
(Master Mode, CKE = 0) ................................... 410
(Master Mode, CKE = 1) ................................... 411
(Slave Mode, CKE = 0) ..................................... 412
DD
2
2
C Bus Data .................................................. 416
C Bus Start/Stop Bits .................................. 416
Rise > T
DD
, V
PWRT
DD
DD
DD
), Case 1 .................................... 50
), Case 2 .................................... 51
Rise Tpwrt) ............................. 50
) ............................................. 51
DD
,
Preliminary
Top-of-Stack Access........................................................... 61
TSTFSZ ............................................................................ 373
Two-Speed Start-up.................................................. 319, 329
Two-Word Instructions
V
V
Voltage Reference Specifications..................................... 401
Voltage Regulator (On-Chip) ............................................ 328
W
Watchdog Timer (WDT)............................................ 319, 326
WCOL ....................................................... 237, 238, 239, 242
WCOL Status Flag.................................... 237, 238, 239, 242
WWW Address ................................................................. 439
WWW, On-Line Support ....................................................... 6
X
XORLW............................................................................. 373
XORWF ............................................................................ 374
DDCORE
Example SPI Slave Mode
External Clock Requirements ................................... 404
I
I
Internal RC Accuracy (INTOSC and INTRC)............ 405
MSSP I
MSSP I
PLL Clock ................................................................. 405
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
Example Cases........................................................... 65
Brown-out Reset (BOR)............................................ 329
Low-Voltage Detection (LVD) ................................... 328
Operation in Sleep Mode .......................................... 329
Power-up Requirements ........................................... 329
Associated Registers ................................................ 327
Control Register........................................................ 326
During Oscillator Failure ........................................... 330
Programming Considerations ................................... 326
2
2
C Bus Data Requirements (Slave Mode) ............... 415
C Bus Start/Stop Bits Requirements
/V
Requirements (CKE = 1) .................................. 413
(Slave Mode) .................................................... 414
Timer, Power-up Timer and Brown-out
Reset Requirements......................................... 407
Requirements ................................................... 408
CAP
2
2
C Bus Data Requirements .......................... 417
C Bus Start/Stop Bits Requirements........... 416
Pin ........................................................... 328
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