PIC18F47J13-I/ML Microchip Technology, PIC18F47J13-I/ML Datasheet - Page 552

• Manufacturer Part Number: PIC18F47J13-I/ML
• Description: IC PIC MCU 128KB FLASH 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F47J13-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 5.5V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DM164128, DM180021, DM183026-2, DV164131, MA180030, DM183022, DM183032, DV164136, MA180024
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J13 FAMILY
SSPOV ............................................................................. 335
SSPOV Status Flag .......................................................... 335
SSPxSTAT Register
SSx ................................................................................... 292
Stack Full/Underflow Resets .............................................. 85
SUBFSR ........................................................................... 479
SUBFWB .......................................................................... 468
SUBLW ............................................................................ 469
SUBULNK ........................................................................ 479
SUBWF ............................................................................ 469
SUBWFB .......................................................................... 470
SWAPF ............................................................................ 470
T
Table Pointer Operations (table) ...................................... 110
Table Reads/Table Writes .................................................. 85
T
TBLRD ............................................................................. 471
TBLWT ............................................................................. 472
Timer0 .............................................................................. 205
Timer1 .............................................................................. 209
Timer2 .............................................................................. 219
DS39974A-page 552
AD
................................................................................... 375
Operation in Power-Managed Modes ...................... 300
Registers .................................................................. 293
Serial Clock .............................................................. 292
Serial Data In ........................................................... 292
Serial Data Out ......................................................... 292
Slave Mode .............................................................. 298
Slave Select ............................................................. 292
Slave Select Synchronization ................................... 298
SPI Clock ................................................................. 297
SSPxBUF Register ................................................... 297
SSPxSR Register ..................................................... 297
Typical Connection ................................................... 296
R/W Bit ............................................................. 315, 318
Associated Registers ............................................... 207
Operation ................................................................. 206
Overflow Interrupt ..................................................... 207
Prescaler .................................................................. 207
Prescaler Assignment (PSA Bit) .............................. 207
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 207
Reads and Writes in 16-Bit Mode ............................ 206
Source Edge Select (T0SE Bit) ................................ 206
Source Select (T0CS Bit) ......................................... 206
16-Bit Read/Write Mode ........................................... 213
Associated Registers ............................................... 218
Clock Source Selection ............................................ 211
Gate ......................................................................... 215
Interrupt .................................................................... 214
Operation ................................................................. 211
Oscillator .......................................................... 209, 213
Resetting, Using the ECCP
TMR1H Register ...................................................... 209
TMR1L Register ....................................................... 209
Use as a Clock Source ............................................. 214
Associated Registers ............................................... 220
Interrupt .................................................................... 220
Operation ................................................................. 219
Output ...................................................................... 220
PR2 Register ............................................................ 266
TMR2 to PR2 Match Interrupt .................................. 266
Switching Assignment ...................................... 207
Layout Considerations ..................................... 214
Special Event Trigger ....................................... 215
Preliminary
Timer3/5 ........................................................................... 221
Timer4
Timer4/6/8 ........................................................................ 233
Timing Diagrams
16-Bit Read/Write Mode .......................................... 226
Associated Registers ............................................... 231
Gate ......................................................................... 226
Operation ................................................................. 225
Oscillator ...........................................................221, 226
Overflow Interrupt .............................................221, 230
Special Event Trigger (ECCP) ................................. 230
TMRxH Register ...................................................... 221
TMRxL Register ....................................................... 221
TMRx to PRx Match Interrupt .................................. 234
Associated Registers ............................................... 235
Interrupt ................................................................... 234
MSSP Clock Shift .................................................... 234
Operation ................................................................. 233
Output ...................................................................... 234
Postscaler. See Postscaler, Timer4/6/8.
Prescaler. See Prescaler, Timer4/6/8.
PRx Register ............................................................ 233
TMRx Register ......................................................... 233
TMRx to PRx Match Interrupt .................................. 233
A/D Conversion ........................................................ 527
Asynchronous Reception ......................................... 358
Asynchronous Transmission .................................... 356
Asynchronous Transmission (Back-to-Back) ........... 356
Automatic Baud Rate Calculation ............................ 354
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 359
Baud Rate Generator with Clock Arbitration ............ 333
BRG Overflow Sequence ......................................... 354
BRG Reset Due to SDAx Arbitration During
Bus Collision During a Repeated
Bus Collision During a Repeated
Bus Collision During a Start
Bus Collision During a Stop Condition (Case 1) ...... 343
Bus Collision During a Stop Condition (Case 2) ...... 343
Bus Collision During Start
Bus Collision for Transmit and Acknowledge .......... 339
CLKO and I/O .......................................................... 510
Clock Synchronization ............................................. 326
Clock/Instruction Cycle .............................................. 86
Enhanced Capture/Compare/PWM ......................... 514
Enhanced PWM Output (Active-High) ..................... 276
Enhanced PWM Output (Active-Low) ...................... 277
EUSARTx Synchronous Receive (Master/Slave) .... 526
EUSARTx Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 518
Example SPI Master Mode (CKE = 1) ..................... 519
Example SPI Slave Mode (CKE = 0) ....................... 520
Example SPI Slave Mode (CKE = 1) ....................... 521
External Clock .......................................................... 508
Fail-Safe Clock Monitor ........................................... 429
First Start Bit ............................................................ 333
Full-Bridge PWM Output .......................................... 280
Half-Bridge PWM Output ..................................278, 285
Normal Operation ............................................ 359
Start Condition ................................................. 341
Start Condition (Case 1) .................................. 342
Start Condition (Case 2) .................................. 342
Condition (SCLx = 0) ....................................... 341
Condition (SDAx Only) ..................................... 340
(Master/Slave) ................................................. 526
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