PIC18F8410-I/PT Microchip Technology, PIC18F8410-I/PT Datasheet - Page 399

• Manufacturer Part Number: PIC18F8410-I/PT
• Description: IC PIC MCU FLASH 8KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8410-I/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Interface: I2C, SPI, USART
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, EUSART, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TBLRD ............................................................................. 325
TBLWT ............................................................................. 326
Time-out in Various Situations (table) ................................ 53
Timer0 .............................................................................. 143
Timer1 .............................................................................. 147
Timer2 .............................................................................. 153
Timer3 .............................................................................. 155
Timing Diagrams
© 2007 Microchip Technology Inc.
16-Bit Mode Timer Reads and Writes ...................... 144
Associated Registers ............................................... 145
Clock Source Edge Select (T0SE Bit) ...................... 144
Clock Source Select (T0CS Bit) ............................... 144
Operation ................................................................. 144
Overflow Interrupt .................................................... 145
Prescaler. See Prescaler, Timer0.
16-Bit Read/Write Mode ........................................... 149
Associated Registers ............................................... 151
Interrupt .................................................................... 150
Low-Power Option ................................................... 149
Operation ................................................................. 148
Oscillator .......................................................... 147, 149
Oscillator Layout Considerations ............................. 150
Overflow Interrupt .................................................... 147
Resetting, Using a Special Event Trigger
TMR1H Register ...................................................... 147
TMR1L Register ....................................................... 147
Use as a Real-Time Clock ....................................... 150
Using as a Clock Source .......................................... 149
Associated Registers ............................................... 154
Interrupt .................................................................... 154
Operation ................................................................. 153
Output ...................................................................... 154
PR2 Register ............................................................ 165
TMR2 to PR2 Match Interrupt .................................. 165
16-Bit Read/Write Mode ........................................... 157
Associated Registers ............................................... 157
Operation ................................................................. 156
Oscillator .......................................................... 155, 157
Overflow Interrupt ............................................ 155, 157
Special Event Trigger (CCP) .................................... 157
TMR3H Register ...................................................... 155
TMR3L Register ....................................................... 155
A/D Conversion ........................................................ 377
Acknowledge Sequence .......................................... 202
Asynchronous Reception ................................. 221, 239
Asynchronous Transmission ............................ 219, 237
Asynchronous Transmission (Back to Back) ... 219, 237
Automatic Baud Rate Calculation ............................ 217
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 223
Baud Rate Generator with Clock Arbitration ............ 196
BRG Overflow Sequence ......................................... 217
BRG Reset Due to SDA Arbitration During
Brown-out Reset (BOR) ........................................... 364
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition
Bus Collision During a Start Condition
Output (CCP) ................................................... 150
Normal Operation ............................................ 223
Start Condition ................................................. 205
Condition (Case 1) ........................................... 206
Condition (Case 2) ........................................... 206
(SCL = 0) ......................................................... 205
(SDA Only) ....................................................... 204
PIC18F6310/6410/8310/8410
Preliminary
Bus Collision During a Stop Condition (Case 1) ...... 207
Bus Collision During a Stop Condition (Case 2) ...... 207
Bus Collision for Transmit and Acknowledge .......... 203
Capture/Compare/PWM (All CCP Modules) ............ 366
CLKO and I/O .......................................................... 361
Clock Synchronization ............................................. 189
Clock/Instruction Cycle .............................................. 67
Example SPI Master Mode (CKE = 0) ..................... 367
Example SPI Master Mode (CKE = 1) ..................... 368
Example SPI Slave Mode (CKE = 0) ....................... 369
Example SPI Slave Mode (CKE = 1) ....................... 370
External Clock (All Modes Except PLL) ................... 359
External Memory Bus for SLEEP
External Memory Bus for SLEEP
External Memory Bus for TBLRD
External Memory Bus for TBLRD
External Memory Bus for TBLRD
External Memory Bus for TBLRD
Fail-Safe Clock Monitor ........................................... 283
High/Low-Voltage Detect (VDIRMAG = 1) ............... 268
High/Low-Voltage Detect Characteristics ................ 356
High/Low-Voltage Detect Operation
I
I
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PSP) Read ............................... 142
Parallel Slave Port (PSP) Write ............................... 141
Program Memory Read ........................................... 362
Program Memory Write ........................................... 363
PWM Output ............................................................ 165
Repeated Start Condition ........................................ 198
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 224
Slave Synchronization ............................................. 175
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 174
SPI Mode (Slave Mode, CKE = 0) ........................... 176
SPI Mode (Slave Mode, CKE = 1) ........................... 176
Synchronous Reception (Master Mode, SREN) ..... 227,
Synchronous Transmission ............................. 225, 240
Synchronous Transmission (Through TXEN) .. 226, 241
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 371
C Bus Start/Stop Bits ............................................ 371
C Master Mode (7 or 10-Bit Transmission) ........... 200
C Master Mode (7-Bit Reception) ......................... 201
C Master Mode First Start Bit ................................ 197
C Slave Mode (10-Bit Reception, SEN = 0) .......... 186
C Slave Mode (10-Bit Reception, SEN = 1) .......... 191
C Slave Mode (10-Bit Transmission) .................... 187
C Slave Mode (7-bit Reception, SEN = 0) ............ 184
C Slave Mode (7-Bit Reception, SEN = 1) ............ 190
C Slave Mode (7-Bit Transmission) ...................... 185
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 202
(16-Bit Microprocessor Mode) ........................... 95
(8-Bit Microprocessor Mode) ............................. 98
(16-Bit Extended Microcontroller Mode) ............ 94
(16-Bit Microprocessor Mode) ........................... 94
(8-Bit Extended Microcontroller Mode) .............. 97
(8-Bit Microprocessor Mode) ............................. 97
(VDIRMAG = 0) ............................................... 267
Sequence (7 or 10-Bit Address Mode) ............ 192
Timer (OST) and Power-up Timer (PWRT) ..... 364
V
242
DD
Rise > T
2
2
C Bus Data ....................................... 373
C Bus Start/Stop Bits ........................ 373
PWRT
) ............................................ 55
DD
DS39635B-page 397
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