PIC24FJ128GA010-I/PT Microchip Technology, PIC24FJ128GA010-I/PT Datasheet - Page 26

• Manufacturer Part Number: PIC24FJ128GA010-I/PT
• Description: IC PIC MCU FLASH 128K 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA010-I/PT

• Core Size: 16-Bit
• Program Memory Size: 128KB (43K x 24)
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC24
• No. Of I/o's: 84
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC24
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164333 - MODULE SKT FOR PM3 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ128GA FAMILY
2.3.2
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operation with the
following data sizes:
1.
2.
3.
4.
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W
rithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
TABLE 2-2:
DS39747C-page 24
(m+1)
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
Instruction
:Wm) for the 32-bit dividend. The divide algo-
ASRF
ASRW
ASRK
LSRF
LSRW
LSRK
ASR
SLF
SLW
SLK
LSR
SL
DIVIDER
INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Arithmetic shift right source register by one bit.
Arithmetic shift right the content of the register by one bit.
Arithmetic shift right source register by up to 15 bits, value held in the W register referenced
within instruction.
Arithmetic shift right source register up to 15 bits. Shift value is literal.
Shift left source register by one bit.
Shift left the content of the file register by one bit.
Shift left source register by up to 15 bits, value held in the W register referenced instruction.
Shift left source register up to 15 bits. Shift value is literal.
Logical shift right source register by one bit.
Logical shift right the content of the register by one bit.
Logical shift right source register by up to 15 bits, value held in the W register referenced
within instruction.
Logical shift right source register up to 15 bits. Shift value is literal.
Preliminary
2.3.3
The PIC24 ALU supports both single-bit and
single-cycle, multi-bit arithmetic and logic shifts.
Multi-bit shifts are implemented using a shifter block,
capable of performing up to a 15-bit arithmetic right
shift, or up to a 15-bit left shift, in a single cycle. All
multi-bit shift instructions only support register direct
addressing for both the operand source and result
destination.
A full summary of instructions that use the shift
operation is provided below in Table 2-2.
Description
MULTI-BIT SHIFT SUPPORT
© 2006 Microchip Technology Inc.