DSPIC33FJ64GP802-I/SP Microchip Technology, DSPIC33FJ64GP802-I/SP Datasheet - Page 135
![IC DSPIC MCU/DSP 64K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ64GP802-I/SP
Manufacturer Part Number
DSPIC33FJ64GP802-I/SP
Description
IC DSPIC MCU/DSP 64K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ64GP802-I/SP
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b, D/A 4x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64GP802-I/SP
Manufacturer:
NIPPON
Quantity:
43 000
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 135 of 412
- Download datasheet (6Mb)
REGISTER 8-5:
REGISTER 8-6:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9-0
Note 1:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
R/W-0
R/W-0
R/W-0
U-0
—
2:
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
Number of DMA transfers = CNT<9:0> + 1.
PAD<15:0>: Peripheral Address Register bits
Unimplemented: Read as ‘0’
CNT<9:0>: DMA Transfer Count Register bits
R/W-0
R/W-0
R/W-0
U-0
—
DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER
DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER
‘1’ = Bit is set
‘1’ = Bit is set
W = Writable bit
W = Writable bit
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
CNT<7:0>
PAD<15:8>
PAD<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
R/W-0
R/W-0
R/W-0
(2)
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
(1)
CNT<9:8>
DS70292E-page 135
(1)
R/W-0
R/W-0
R/W-0
(2)
R/W-0
bit 8
bit 0
bit 8
bit 0
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