DSPIC33FJ64GP802-I/SP Microchip Technology, DSPIC33FJ64GP802-I/SP Datasheet - Page 141
![IC DSPIC MCU/DSP 64K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ64GP802-I/SP
Manufacturer Part Number
DSPIC33FJ64GP802-I/SP
Description
IC DSPIC MCU/DSP 64K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ64GP802-I/SP
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b, D/A 4x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64GP802-I/SP
Manufacturer:
NIPPON
Quantity:
43 000
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 141 of 412
- Download datasheet (6Mb)
9.0 OSCILLATOR CONFIGURATION
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 oscillator system
provides:
FIGURE 9-1:
© 2011 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
SOSCO
Note 1: This
SOSCI
Note 1:
R
(2)
2: Some registers and associated bits
2:
3:
OSC1
OSC2
features of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Section 39. Oscillator
(Part III)” (DS70216) of the “dsPIC33F/
PIC24H
which is available from the Microchip
website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to
“Memory Organization”
sheet for device-specific register and bit
information.
See
If the Oscillator is used with XT or HS modes, an extended parallel resistor with the value of 1 MΩ must be connected.
The term F
this document F
Doze mode is used in any ratio other than 1:1, which is the default.
Secondary Oscillator
Primary Oscillator
Oscillator
Figure 9-2
Oscillator
TUN<5:0>
LPRC
data
FRC
POSCMD<1:0>
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 OSCILLATOR SYSTEM DIAGRAM
Family
P
refers to the clock source for all the peripherals, while F
LPOSCEN
for PLL details.
sheet
CY
Auxiliary Oscillator
and F
Reference
P
summarizes
are used interchangeably, except in the case of Doze mode. F
POSCCLK
S1
S3
÷ 16
in this data
families
Section 4.0
FRCDIV<2:0>
Manual”,
AOSCMD<1:0>
AOSCCLK
and
the
POSCCLK
of
PLL
ASRCSEL
XTPLL, HSPLL,
ECPLL, FRCPLL
F
• External and internal oscillator options as clock
• An on-chip Phase-Locked Loop (PLL) to scale the
• An internal FRC oscillator that can also be used
• Clock switching between various clock sources
• Programmable clock postscaler for system power
• A Fail-Safe Clock Monitor (FSCM) that detects
• An Oscillator Control register (OSCCON)
• Non-volatile Configuration bits for main oscillator
• An auxiliary crystal oscillator for Audio DAC
A simplified diagram of the oscillator system is shown
in
VCO
Clock Fail
sources
internal operating frequency to the required
system clock frequency
with the PLL, thereby allowing full-speed operation
without any external clock generation hardware
savings
clock failure and takes fail-safe measures
selection
Figure
S7
XT, HS, EC
(1)
FRCDIV16
CY
FRCDIVN
refers to the clock source for the CPU. Throughout
F
SOSC
LPRC
FRC
VCO
9-1.
(1)
SELACK
Clock Switch
NOSC<2:0> FNOSC<2:0>
S1/S3
S7
S0
S5
S4
S2
S6
P
÷ 2
and F
Reset
CY
APSTSCLR<2:0>
DOZE<2:0>
will be different when
÷ N
DS70292E-page 141
ACLK
WDT, PWRT,
Timer1
FSCM
DAC
F
F
F
OSC
P
CY
(3)
(3)
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