DSPIC33FJ64GP802-I/SP Microchip Technology, DSPIC33FJ64GP802-I/SP Datasheet - Page 208
![IC DSPIC MCU/DSP 64K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ64GP802-I/SP
Manufacturer Part Number
DSPIC33FJ64GP802-I/SP
Description
IC DSPIC MCU/DSP 64K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ64GP802-I/SP
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b, D/A 4x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64GP802-I/SP
Manufacturer:
NIPPON
Quantity:
43 000
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 208 of 412
- Download datasheet (6Mb)
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 17-1:
DS70292E-page 208
SDAx
SCLx
I
2
C™ BLOCK DIAGRAM (
Shift Clock
Shift
Clock
BRG Down Counter
Match Detect
Start and Stop
Start and Stop
Bit Generation
Acknowledge
Generation
I2CxRCV
I2CxRSR
I2CxADD
Stretching
Bit Detect
I2CxTRN
Collision
Reload
Control
Detect
Clock
T
CY
/2
LSb
LSb
X
Address Match
= 1)
I2CxBRG
I2CxSTAT
I2CxCON
I2CxMSK
© 2011 Microchip Technology Inc.
Write
Read
Write
Read
Data Bus
Internal
Write
Read
Write
Read
Write
Read
Write
Read
Read
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