DSPIC33FJ128GP306A-I/PT Microchip Technology, DSPIC33FJ128GP306A-I/PT Datasheet - Page 157
![IC DSPIC MCU/DSP 128K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
DSPIC33FJ128GP306A-I/PT
Manufacturer Part Number
DSPIC33FJ128GP306A-I/PT
Description
IC DSPIC MCU/DSP 128K 64-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128GP306A-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
64-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
53
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
53
Flash Memory Size
128KB
Supply Voltage Range
3V To 3.6V
Rohs Compliant
No
Package
64TQFP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
I2C/SPI/UART
On-chip Adc
18-chx10-bit|18-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP306A-I/PT
Manufacturer:
RENESAS
Quantity:
450
Company:
Part Number:
DSPIC33FJ128GP306A-I/PT
Manufacturer:
MICROCHIP
Quantity:
3 100
Company:
Part Number:
DSPIC33FJ128GP306A-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
9.2
Applications are free to switch between any of the four
clock sources (Primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects
dsPIC33FJXXXGPX06A/X08A/X10A devices have a
safeguard lock built into the switch process.
9.2.1
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register must be programmed to
‘0’. (Refer to
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
The NOSC control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSC bits (OSCCON<14:12>)
reflect the clock source selected by the FNOSC
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
9.2.2
At a minimum, performing a clock switch requires this
basic sequence:
1.
2.
3.
4.
5.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1.
© 2011 Microchip Technology Inc.
Note:
If
(OSCCON<14:12>) to determine the current
oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register high byte.
Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
Perform the unlock sequence to allow a write to
the OSCCON register low byte.
Set the OSWEN bit to initiate the oscillator
switch.
The clock switching hardware compares the
COSC status bits with the new value of the
NOSC control bits. If they are the same, then the
clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
Clock Switching Operation
that
desired,
ENABLING CLOCK SWITCHING
OSCILLATOR SWITCHING SEQUENCE
Primary Oscillator mode has three different
submodes (XT, HS and EC) which are
determined
Configuration bits. While an application
can switch to and from Primary Oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
Section 22.1 “Configuration Bits”
could
read
result
dsPIC33FJXXXGPX06A/X08A/X10A
by
the
the
from
POSCMD<1:0>
COSC
this
flexibility,
bits
for
2.
3.
4.
5.
6.
9.3
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Note 1: The processor continues to execute code
If a valid clock switch has been initiated, the sta-
tus
(OSCCON<3>) are cleared.
The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or LP (if LPOSCEN remains set).
2: Direct clock switches between any pri-
3: Refer
Fail-Safe Clock Monitor (FSCM)
bits,
throughout the clock switching sequence.
Timing sensitive code should not be
executed during this time.
mary oscillator mode with PLL and FRC-
PLL mode are not permitted. This applies
to clock switches in either direction. In
these instances, the application must
switch to FRC mode as a transition clock
source between the two PLL modes.
(DS70186) in the “dsPIC33F/PIC24H
Family Reference Manual” for details.
LOCK
to
(OSCCON<5>)
Section
DS70593C-page 157
7.
“Oscillator”
and
CF