DSPIC33FJ128GP306A-I/PT Microchip Technology, DSPIC33FJ128GP306A-I/PT Datasheet - Page 341

IC DSPIC MCU/DSP 128K 64-TQFP

DSPIC33FJ128GP306A-I/PT

Manufacturer Part Number
DSPIC33FJ128GP306A-I/PT
Description
IC DSPIC MCU/DSP 128K 64-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP306A-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
64-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
53
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
53
Flash Memory Size
128KB
Supply Voltage Range
3V To 3.6V
Rohs Compliant
No
Package
64TQFP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
I2C/SPI/UART
On-chip Adc
18-chx10-bit|18-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Revision C (March 2011)
This revision includes typographical and formatting
changes throughout the data sheet text. In addition, all
instances of V
All other major changes are referenced by their
respective section in the following table.
TABLE B-2:
© 2011 Microchip Technology Inc.
Section 2.0 “Guidelines for Getting Started
with 16-Bit Digital Signal Controllers”
Section 4.0 “Memory Organization”
Section 9.0 “Oscillator Configuration”
Section 21.0 “10-Bit/12-Bit
Analog-to-Digital Converter (ADC)”
Section 22.0 “Special Features”
DDCORE
Section Name
MAJOR SECTION UPDATES
have been removed.
dsPIC33FJXXXGPX06A/X08A/X10A
Updated the title of
Connection
The frequency limitation for device PLL start-up conditions was
updated in
Start-up”.
The second paragraph in
The All Resets values for the following SFRs in the Timer Register
Map were changed (see
• TMR1
• TMR2
• TMR3
• TMR4
• TMR5
• TMR6
• TMR7
• TMR8
• TMR9
Added Note 3 to the OSCCON: Oscillator Control Register (see
Register
Added Note 2 to the CLKDIV: Clock Divisor Register (see
Register
Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see
Register
Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see
Register
Updated the V
(see
Added a new paragraph and removed the third paragraph in
Section 22.1 “Configuration
Added the column “RTSP Effects” to the Configuration Bits
Descriptions (see
Figure
9-1).
9-2).
9-3).
9-4).
Section 2.7 “Oscillator Value Conditions on Device
21-1).
(Vcap)”.
REFL
Table
Section 2.3 “CPU Logic Filter Capacitor
references in the ADC1 module block diagram
Update Description
22-2).
Table
Section 2.9 “Unused I/Os”
Bits”.
4-6):
DS70593C-page 341
was updated.

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