DSPIC33FJ128GP306A-I/PT Microchip Technology, DSPIC33FJ128GP306A-I/PT Datasheet - Page 254

• Manufacturer Part Number: DSPIC33FJ128GP306A-I/PT
• Description: IC DSPIC MCU/DSP 128K 64-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP306A-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 53
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: No
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Interface Type: I2C/SPI/UART
• On-chip Adc: 18-chx10-bit|18-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJXXXGPX06A/X08A/X10A
TABLE 22-2:
DS70593C-page 254
POSCMD<1:0>
FNOSC<2:0>
FCKSM<1:0>
OSCIOFNC
WDTPOST
WDTPRE
FWDTEN
Bit Field
PLLKEN
WINDIS
GWRP
IESO
ds
FOSCSEL Immediate Two-speed Oscillator Start-up Enable bit
FOSCSEL
Register
FOSC
FOSC
FWDT
FWDT
FWDT
FWDT
FWDT
FOSC
PIC33FJXXXGPX06A/X08A/X10A
FGS
Immediate Clock Switching Mode bits
Immediate General Segment Write-Protect bit
Immediate
Immediate OSC2 Pin Function bit (except in XT and HS modes)
Immediate Primary Oscillator Mode Select bits
Immediate Watchdog Timer Enable bit
Immediate Watchdog Timer Window Enable bit
Immediate PLL Lock Enable bit
Immediate Watchdog Timer Prescaler bit
Immediate Watchdog Timer Postscaler bits
otherwise,
switch is
enabled,
effect is
If clock
on any
device
Reset;
Effect
RTSP
RTSP
1 = User program memory is not write-protected
0 = User program memory is write-protected
1 = Start-up device with FRC, then automatically switch to the user-selected
0 = Start-up device with user-selected oscillator source
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRC) oscillator with postscaler
110 = Internal Fast RC (FRC) oscillator with divide-by-16
101 = LPRC oscillator
100 = Secondary (LP) oscillator
011 = Primary (XT, HS, EC) oscillator with PLL
010 = Primary (XT, HS, EC) oscillator
001 = Internal Fast RC (FRC) oscillator with PLL
000 = FRC oscillator
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
11 = Primary oscillator disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
0 = Watchdog Timer enabled/disabled by user software (LPRC can be dis-
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
1 = Clock switch to PLL source will wait until the PLL lock signal is valid.
0 = Clock switch will not wait for the PLL lock signal.
1 = 1:128
0 = 1:32
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
oscillator source when ready
Clearing the SWDTEN bit in the RCON register will have no effect.)
abled by clearing the SWDTEN bit in the RCON register)
CONFIGURATION BITS DESCRIPTION (CONTINUED)
Description
© 2011 Microchip Technology Inc.