PIC18F4320-I/P Microchip Technology, PIC18F4320-I/P Datasheet - Page 337

• Manufacturer Part Number: PIC18F4320-I/P
• Description: IC MCU FLASH 4KX16 A/D 40-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4320-I/P

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X20)
FIGURE 26-13:
© 2007 Microchip Technology Inc.
62
63
64
65
66
Param.
No.
(CKP = 0)
(CKP = 1)
SDI
SS
SCK
SCK
SDO
Note:
T
T
T
T
T
WR
RD
RD
IBF
DT
Symbol
Refer to Figure 26-5 for load conditions.
V2
L2
H2
INH
H2
WR
DT
DT
DT
V RD ↓ and CS ↓ to Data–Out Valid
I
H Data In Valid Before WR ↑ or CS ↑
I WR ↑ or CS ↑ to Data–In
(setup time)
Invalid (hold time)
RD ↑ or CS ↓ to Data–Out Invalid
Inhibit of the IBF Flag bit being Cleared from
WR ↑ or CS ↑
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
70
80
71
73
MSb In
Characteristic
MSb
74
72
PIC18F2220/2320/4220/4320
75, 76
PIC18FXX20
PIC18LFXX20
bit 6 - - - - - -1
bit 6 - - - -1
78
79
Min
20
20
35
10
—
—
LSb
3 T
79
78
Max
80
30
—
—
—
LSb In
CY
Units
ns
ns
ns
ns
ns
DS39599G-page 335
Conditions