PIC18F4320-I/P Microchip Technology, PIC18F4320-I/P Datasheet - Page 41

• Manufacturer Part Number: PIC18F4320-I/P
• Description: IC MCU FLASH 4KX16 A/D 40-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4320-I/P

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 3-3:
© 2007 Microchip Technology Inc.
Primary System
Clock
(PRI_IDLE mode)
T1OSC or INTRC
INTOSC
Sleep mode
Note 1:
Power-Managed
2:
3:
4:
5:
Clock in
Mode
(2)
In this instance, refers specifically to the INTRC clock source.
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
Two-Speed Start-up is covered in greater detail in Section 23.3 “Two-Speed Start-up”.
Execution continues during the INTOSC stabilization period.
Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).
ACTIVITY AND EXIT DELAY ON WAKE-UP FROM SLEEP MODE OR
ANY IDLE MODE (BY CLOCK SOURCES)
(1)
LP, XT, HS
HSPLL
EC, RC, INTRC
INTOSC
LP, XT, HS
HSPLL
EC, RC, INTRC
INTOSC
LP, XT, HS
HSPLL
EC, RC, INTRC
INTOSC
LP, XT, HS
HSPLL
EC, RC, INTRC
INTOSC
Primary System
Clock
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
Power-Managed
Mode Exit Delay
OST + 2 ms
OST + 2 ms
OST + 2 ms
PIC18F2220/2320/4220/4320
5-10 μs
5-10 μs
5-10 μs
5-10 μs
5-10 μs
5-10 μs
None
OST
OST
OST
(5)
(5)
(4)
(5)
(5)
(4)
Clock Ready
(OSCCON)
Status Bit
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS
—
—
—
—
CPU and peripherals
clocked by primary clock
and executing
instructions.
CPU and peripherals
clocked by selected
power-managed mode
clock and executing
instructions until primary
clock source becomes
ready.
Not clocked or
Two-Speed Start-up (if
enabled) until primary
clock source becomes
ready
Exit by Interrupt
Activity During Wake-up from
(3)
.
Power-Managed Mode
DS39599G-page 39
Not clocked or
Two-Speed
Start-up
(if enabled)
Exit by Reset
(3)
.