DSPIC33FJ128GP706-I/PT Microchip Technology, DSPIC33FJ128GP706-I/PT Datasheet - Page 292

IC DSPIC MCU/DSP 128K 64TQFP

DSPIC33FJ128GP706-I/PT

Manufacturer Part Number
DSPIC33FJ128GP706-I/PT
Description
IC DSPIC MCU/DSP 128K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP706-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
64-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
53
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Data Rom Size
4096 B
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ128GP706-I/PT
Manufacturer:
MICROCHIP
Quantity:
150
Part Number:
DSPIC33FJ128GP706-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC33FJ128GP706-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
23.0
dsPIC33F devices include several features intended to
maximize application flexibility and reliability, and mini-
mize cost through elimination of external components.
These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
23.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
TABLE 23-1:
© 2006 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF8004
0xF8006
0xF8008
0xF800A
0xF800C
0xF800E
0xF8010
0xF8012
0xF8014
0xF8016
Note 1:
Address
Note:
2:
3:
4:
SPECIAL FEATURES
Configuration Bits
FGS
FOSCSEL
FOSC
FWDT
FPOR
RESERVED3
FUID0
FUID1
FUID2
FUID3
On the dsPIC33F General Purpose Family devices (dsPIC33FJXXXGPXXX), these bits are reserved (read as ‘1’ and
must be programmed as ‘1’).
These reserved bits read as ‘1’ and must be programmed as ‘1’.
Unimplemented bits are read as ‘0’.
This reserved bit is a read-only copy of the GCP bit.
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
Name
DEVICE CONFIGURATION REGISTER MAP
PWMPIN
FWDTEN
IESO
Bit 7
FCKSM<1:0>
RBS<1:0>
RSS<1:0>
(1)
WINDIS
HPOL
Bit 6
(1)
Preliminary
LPOL
TEMP
Bit 5
(1)
The device Configuration register map is shown in
Table 23-1.
The individual Configuration bit descriptions for the
FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and
FICD Configuration registers are shown in Table 23-2.
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF) which can only be
accessed using table reads and table writes.
The upper byte of all device Configuration registers
should always be ‘1111
appear to be NOP instructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’s to these locations
has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
Bit 4
Reserved
(2)
Bit 3
BSS<2:0>
SSS<2:0>
OSCIOFNC
WDTPOST<3:0>
GSS1
Bit 2
1111’. This makes them
dsPIC33F
FPWRT<2:0>
DS70165D-page 289
GSS0
POSCMD<1:0>
Bit 1
BWRP
SWRP
GWRP
Bit 0

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