AT89C5131A-S3SUM Atmel, AT89C5131A-S3SUM Datasheet - Page 137

• Manufacturer Part Number: AT89C5131A-S3SUM
• Description: IC 8051 MCU FLASH 32K USB 52PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• Package: 52PLCC
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 48 MHz
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

21.10.2
4337K–USB–04/08
USB Interrupt Control System
As shown in Figure 21-16, many events can produce a USB interrupt:
• TXCMPL: Transmitted In Data (see
• RXOUTB0: Received Out Data Bank 0 (see
• RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (see
• RXSETUP: Received Setup (see
• STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (see
• SOFINT: Start of Frame Interrupt
• WUPCPU: Wake-Up CPU Interrupt
• SPINT: Suspend Interrupt
when the Host accept a In packet.
hardware when an Out packet is accepted by the endpoint and stored in bank 0.
page
stored in bank 1.
an SETUP packet is accepted by the endpoint.
144). This bit is set by hardware when a STALL handshake has been sent as requested by
STALLRQ, and is reset by hardware when a SETUP packet is received.
Interrupt Enable Register” on page
Frame packet has been received.
Interrupt Enable Register” on page
detected on the USB bus, after a SUSPEND state.
Enable Register” on page
on the USB bus.
144). This bit is set by hardware when an Out packet is accepted by the endpoint and
141.). This bit is set by hardware when a USB suspend is detected
(See “USBIEN Register USBIEN (S:BEh) USB Global Interrupt
(See “USBIEN Register USBIEN (S:BEh) USB Global
Table 21-9 on page
141.). This bit is set by hardware when a USB Start of
141.). This bit is set by hardware when a USB resume is
(See “USBIEN Register USBIEN (S:BEh) USB Global
Table 21-9 on page
Table 21-9 on page
144). This bit is set by hardware when
AT89C5130A/31A-M
144). This bit is set by hardware
144). This bit is set by
Table 21-9 on page
Table 21-9 on
137