DSPIC30F5013-20I/PT Microchip Technology, DSPIC30F5013-20I/PT Datasheet
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... Microchip Technology Inc. dsPIC30F5011/5013 Data Sheet High-Performance, 16-bit Digital Signal Controllers DS70116H ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructions are single cycle - Multiply-Accumulate (MAC) operation • Single cycle ±16 shift © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • Low power consumption dsPIC30F5011/5013 Controller Family Program Memory Device Pins Bytes Instructions dsPIC30F5011 64 66K 22K dsPIC30F5013 80 66K 22K DS70116H-page 4 Output SRAM EEPROM Timer Input Comp/Std Bytes Bytes ...
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... SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F5011 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 ...
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... DD INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70116H-page dsPIC30F5013 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 U1RX/RF2 U1TX/RF3 © ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 DS70116H-page 7 ...
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... NOTES: DS70116H-page 8 © 2008 Microchip Technology Inc. ...
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... Digital Signal Controller (DSC) devices. The dsPIC30F5011/5013 devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for dsPIC30F5011 and dsPIC30F5013, respectively. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 DS70116H-page 9 ...
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... OSC2/CLKO/RC15 PORTC EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 OC5/IC5/CN13/RD4 OC6/IC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/RD7 IC1/INT1/RD8 IC2/INT2/RD9 IC3/INT3/RD10 IC4/INT4/RD11 PORTD C1RX/RF0 C1TX/RF1 U1RX/SDI1/RF2 EMUD3/U1TX/SDO1/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 PORTF C2RX/RG0 C2TX/RG1 SCL/RG2 SDA/RG3 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SS2/CN11/RG9 CSDI/RG12 CSDO/RG13 CSCK/RG14 COFS/RG15 PORTG © 2008 Microchip Technology Inc. ...
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... FIGURE 1-2: dsPIC30F5013 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU Program Counter Stack Address Latch Control Logic Program Memory (66 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch 24 16 Instruction Decode & Control ...
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... Master Clear (Reset) input or programming voltage input. This pin is an active low Reset to the device. ST Compare Fault A input (for Compare channels and 4). ST Compare Fault B input (for Compare channels and 8). — Compare outputs 1 through 8. Analog = Analog input O = Output P = Power Description © 2008 Microchip Technology Inc. ...
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... I REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Buffer Type ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... NOTES: DS70116H-page 14 © 2008 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 There are two methods of accessing data stored in program memory: • The upper 32 Kbytes of data space memory can ...
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... The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit. 2.2.3 PROGRAM COUNTER The program counter is 23 bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. © 2008 Microchip Technology Inc. ...
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... DSP AccA Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2008 Microchip Technology Inc. dsPIC30F5011/5013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 ...
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... The REPEAT loop count must be setup for 18 iterations of the DIV/DIVF instruction. Thus, a complete divide operation requires 19 cycles. Note: The divide flow is interruptible. However, the user needs to save the context as appropriate. Function © 2008 Microchip Technology Inc. ...
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... MAC MAC MOVSAC MPY MPY.N MSC © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: • Fractional or integer DSP multiply (IF) • Signed or unsigned DSP multiply (US) • ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70116H-page 20 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2008 Microchip Technology Inc. ...
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... B) as its pre-accumulation source and post-accumulation desti- nation. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2.4.2.1 Adder/Subtracter, Overflow and Saturation ...
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... Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2008 Microchip Technology Inc. ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70116H-page 24 © 2008 Microchip Technology Inc. ...
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... TBLPAG<7> to determine user or configuration space access. In Table 3-1, Program Space Address Construction, bit 23 allows access to the Device ID, the User ID and the Configuration bits. Otherwise, bit 23 is always clear. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 FIGURE 3-1: PROGRAM SPACE MEMORY MAP ...
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... Program space visibility cannot be used to access bits <23:16> word in program memory. DS70116H-page 26 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA PSVPAG Reg 8 bits 15 bits EA TBLPAG Reg 8 bits 16 bits 24-bit EA <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> Data EA<15:0> Data EA<14:0> 0 Byte Select © 2008 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) © 2008 Microchip Technology Inc. dsPIC30F5011/5013 A set of table instructions are provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the lsw of the program address; ...
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... Execution in the last iteration - Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle © 2008 Microchip Technology Inc. ...
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... The core has two data spaces. The data spaces can be considered either separate (for instructions one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 0x0000 (1) PSVPAG 0x01 8 0x8000 23 ...
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... The X data space is used by all instructions and supports all Addressing modes, as shown in Figure 3-7. LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0FFE 0x1000 Y Data RAM (Y) 0x17FE 0x1800 0x1FFE 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2008 Microchip Technology Inc. ...
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... FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2008 Microchip Technology Inc. dsPIC30F5011/5013 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops (Read) ...
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... FIGURE 3-8: MSB 15 0001 Byte1 Byte3 0003 0x0000 Byte5 0x0000 0005 0x0000 backward compatibility with DATA ALIGNMENT LSB 0000 Byte 0 Byte 2 0002 Byte 4 0004 © 2008 Microchip Technology Inc. ...
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... MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 There is a Stack Pointer Limit register (SPLIM) associated with the Stack Pointer ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV ...
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... NOTES: DS70116H-page 36 © 2008 Microchip Technology Inc. ...
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... The INTCON2 register controls the external interrupt request signal behavior and the use of the alternate vector table. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 • INTTREG<15:0> The associated interrupt vector number and the new CPU interrupt priority level are latched into vector number (VECNUM< ...
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... OC8 – Output Compare INT3 – External Interrupt INT4 – External Interrupt – Combined IRQ for CAN2 39-40 47-48 Reserved 41 49 DCI – Codec Transfer Done 42 50 LVD – Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority © 2008 Microchip Technology Inc. ...
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... A momentary dip in the power supply to the device has been detected which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 4.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 4-1 ...
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... Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector — — — Interrupt 52 Vector Interrupt 53 Vector © 2008 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 0x00007E 0x000080 0x000082 0x000084 0x000094 0x0000FE ...
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... The RETFIE (return from interrupt) instruction will unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 4.5 Alternate Vector Table In program memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 4-1 ...
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TABLE 4-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
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... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2008 Microchip Technology Inc. dsPIC30F5011/5013 5.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buffers that have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode (i.e., address boundary checks are performed on both the lower and upper address boundaries). © 2008 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2008 Microchip Technology Inc. dsPIC30F5011/5013 5.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control registers: register MODCON<15:0> contains enable flags as well register field to specify the W address registers. ...
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... W register that has been designated as the bit-reversed pointer. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer N bytes, addressing and bit-reversed © 2008 Microchip Technology Inc. ...
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... TABLE 5-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 5-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 2048 1024 512 256 128 © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value A0 Decimal 0x0400 ...
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... NOTES: DS70116H-page 48 © 2008 Microchip Technology Inc. ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. dsPIC30F5011/5013 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 6.6 “Programming Operations” for further details. DD Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2008 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2008 Microchip Technology Inc. dsPIC30F5011/5013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, the ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2008 Microchip Technology Inc. ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — ...
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... NOTES: DS70116H-page 54 © 2008 Microchip Technology Inc. ...
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... A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires complete but the write time will vary with voltage and temperature. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is ...
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... Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2008 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... The NVMADR captures last table access address. ; Select data EEPROM for multi word op ; Operate Key to allow program operation ; Block all interrupts with priority <7 for ; next 5 instructions ; Write the 0x55 key ; Write the 0xAA key ; Start write cycle © 2008 Microchip Technology Inc. ...
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... This should be used in applications where excessive writes can stress bits near the specification limit. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
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... NOTES: DS70116H-page 60 © 2008 Microchip Technology Inc. ...
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... WR TRIS WR LAT + WR Port Read LAT Read Port © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... NOP EXAMPLE 8-1: MOV 0xFF00, W0 MOV W0, TRISB NOP btss PORTB, #13 I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> as outputs ; additional instruction cycle ; bit test RB13 and skip if set © 2008 Microchip Technology Inc. ...
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... LATC15 LATC14 LATC13 — Legend: — = unimplemented, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-4: PORTC REGISTER MAP FOR dsPIC30F5013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISC 02CC TRISC15 TRISC14 TRISC13 — ...
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... LATD11 Legend: — = unimplemented, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-6: PORTD REGISTER MAP FOR dsPIC30F5013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISD 02D2 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 ...
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... TABLE 8-8: PORTF REGISTER MAP FOR dsPIC30F5013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name TRISF 02DE — — — — PORTF 02E0 — — — — LATF 02E2 — — — — Legend: — = unimplemented, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. ...
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... Legend: — = unimplemented, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-13: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5013 (BITS 7-0) SFR Addr. Bit 7 Bit 6 Name CNEN1 00C0 CN7IE ...
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... TGATE SOSCO/ T1CK LPOSCEN SOSCI © 2008 Microchip Technology Inc. dsPIC30F5011/5013 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... Low power • Real-Time clock interrupts These operating modes are determined by setting the appropriate bit(s) in the T1CON Control register. FIGURE 9-2: RECOMMENDED COMPONENTS FOR TIMER1 LP OSCILLATOR RTC C1 32.768 kHz XTAL pF 100K © 2008 Microchip Technology Inc. SOSCI dsPIC30FXXXX SOSCO ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt will be generated if enabled ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented, read as ‘0’ Note 1: ...
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... Interrupt on a 32-bit period register match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer ...
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... Timer Configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70116H-page TMR3 TMR2 MSB LSB Comparator x 32 PR3 PR2 TGATE (T2CON<6> Gate Sync ’ for a 32-bit timer/counter operation. All control Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2008 Microchip Technology Inc. ...
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... Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2008 Microchip Technology Inc. dsPIC30F5011/5013 PR2 Comparator x 16 TMR2 TGATE TON 1 x Gate Sync PR3 Comparator x 16 ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). © 2008 Microchip Technology Inc. ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70116H-page 76 © 2008 Microchip Technology Inc. ...
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... T4CK Note: Timer Configuration bit T32 (T4CON<3>) must be set to ‘ bits are respective to the T4CON register. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 • The Timer4/5 module does not support the ADC event trigger feature • Timer4/5 can not be utilized by other peripheral ...
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... Timer5: TCS = 1 (16-bit counter) TCS = 0, TGATE = 1 (gated time accumulation) DS70116H-page 78 PR4 Comparator x 16 TMR4 TGATE TON 1 x Gate Sync PR5 Comparator x 16 TMR5 TGATE Sync Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2008 Microchip Technology Inc. ...
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TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
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... NOTES: DS70116H-page 80 © 2008 Microchip Technology Inc. ...
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... ICBNE, ICOV ICxCON Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 12.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • ...
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... Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx Status register. Enabling an interrupt is accomplished via the respective capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. © 2008 Microchip Technology Inc. defined as ...
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TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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... NOTES: DS70116H-page 84 © 2008 Microchip Technology Inc. ...
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... TMR2<15:0 TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Fault condition has occurred. This state will be maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been reenabled by writing to the appropriate control bits © 2008 Microchip Technology Inc. ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
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TABLE 13-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS ...
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... If any transmit data has been written to the buffer register, the contents of the © 2008 Microchip Technology Inc. dsPIC30F5011/5013 transmit buffer are moved to SPIxSR. The received data is thus placed in SPIxBUF and the transmit data in SPIxSR is ready for the next transfer ...
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... Clock Clock Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Secondary Primary F Prescaler CY Prescaler 1:1 – 1 16, 64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2008 Microchip Technology Inc. ...
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... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 14.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT< ...
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TABLE 14-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented, read ...
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... Thus, the I C module can operate either as a slave master bus. FIGURE 15-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2008 Microchip Technology Inc. dsPIC30F5011/5013 15.1.1 VARIOUS I The following types • slave operation with 7-bit address 2 • slave operation with 10-bit address 2 • ...
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... LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2008 Microchip Technology Inc. ...
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... SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 15.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 96
... C bus have de-asserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. © 2008 Microchip Technology Inc. 2 CRCV ...
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... Generate a Stop condition on SDA and SCL. 2 • Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2 15. Master Operation The master device generates all of the serial clock ...
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... C OPERATION DURING CPU IDLE MODE 2 For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle bus © 2008 Microchip Technology Inc. ...
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TABLE 15- REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN ...
Page 100
... NOTES: DS70116H-page 100 © 2008 Microchip Technology Inc. ...
Page 101
... Internal Data Bus UTXBRK Data UxTX Parity Note © 2008 Microchip Technology Inc. dsPIC30F5011/5013 16.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
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... Receive Buffer Control 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA – Generate Flags – Generate Interrupt – Shift Data Characters Control Signals UxRXIF © 2008 Microchip Technology Inc. ...
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... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2008 Microchip Technology Inc. dsPIC30F5011/5013 16.3 Transmitting Data 16.3.1 ...
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... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. © 2008 Microchip Technology Inc. RXB) ...
Page 105
... FERR bit set. The break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 16.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
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... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. © 2008 Microchip Technology Inc. ...
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TABLE 16-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG ...
Page 108
... NOTES: DS70116H-page 108 © 2008 Microchip Technology Inc. ...
Page 109
... Programmable link to Input Capture module (IC2, for both CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 110
... Acceptance Filter c RXF3 c Acceptance Filter e RXF4 p t Acceptance Filter RXF5 R M Identifier Data Field Receive RERRCNT Error Counter TERRCNT Transmit Err Pas Error Bus Off Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator (1) CiRX © 2008 Microchip Technology Inc. ...
Page 111
... Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 112
... End-of-Frame (EOF) field. Reading the RXnIF flag will indicate which receive buffer caused the interrupt. • Wake-up Interrupt: The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. © 2008 Microchip Technology Inc. ...
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... SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority ...
Page 114
... definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 μsec corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point . Also, by definition, Q Sync © 2008 Microchip Technology Inc. ...
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... Phase2 Seg is initialized by setting SEG2PH<2:0> (CiCFG2<10:8>). The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg > = Phase2 Seg © 2008 Microchip Technology Inc. dsPIC30F5011/5013 17.6.5 SAMPLE POINT The sample point is the point of time at which the bus ...
Page 116
TABLE 17-1: CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1RXF0SID 0300 — — — C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier <5:0> C1RXF1SID 0308 — ...
Page 117
TABLE 17-1: CAN1 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1B2 0358 Transmit Buffer 1 Byte 3 C1TX1B3 035A Transmit Buffer 1 Byte 5 C1TX1B4 035C Transmit Buffer 1 Byte 7 C1TX1CON ...
Page 118
... NOTES: DS70116H-page 118 © 2008 Microchip Technology Inc. ...
Page 119
... CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 18.2.3 CSDI PIN The serial data input (CSDI) pin is configured as an input only pin when the module is enabled ...
Page 120
... DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70116H-page 120 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer Control Unit 15 DCI Shift Register SCKD CSCK FSD COFS 0 CSDI CSDO © 2008 Microchip Technology Inc. ...
Page 121
... Note: The COFSG control bits will have no effect in AC-Link mode since the frame length is set to 256 CSCK periods by the protocol. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 18.3.4 FRAME SYNC MODE CONTROL BITS The type of frame sync signal is selected using the ...
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... LSB S12 S12 S12 Tag Tag Tag bit 2 bit 1 LSb MSb bit 14 bit 13 MSB LSB MSB 2 S protocol does not specify word length – this LSB © 2008 Microchip Technology Inc. ...
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... When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the operation of the DCI module. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 EQUATION 18-2: The required bit clock frequency will be determined by the system sampling rate and frame size. Typical bit ...
Page 124
... Furthermore, assume that data is only received during slot #0 but is transmitted during slot #0 and slot #1. In this case, the buffer control unit counter would be incremented twice during a data frame but only one receive register location would be filled with data. © 2008 Microchip Technology Inc. ...
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... In these situations, the user should poll the SLOT status bits to determine what data should be loaded into the buffer registers to resynchronize the software with the DCI module. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 18.3.16 TRANSMIT STATUS BITS There are two transmit status bits in the DCISTAT SFR. ...
Page 126
... LSbs of the data word are set to ‘0’ by the module. This truncation of the time slots limits the A/D and DAC data to 16 bits but permits proper data alignment in the TXBUF and RXBUF registers. Each RXBUF and TXBUF register will contain one data time slot value. © 2008 Microchip Technology Inc. ...
Page 127
... TSCON and RSCON SFRs. Since the total available buffer length is 64 bits, it would take 4 consecutive interrupts to transfer the AC-Link frame. The application software must keep track of the current AC-Link frame segment. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2 18.7 I ...
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TABLE 18-2: DCI REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 DCICON1 0240 DCIEN — DCISIDL — DCICON2 0242 — — — — DCICON3 0244 — — — — DCISTAT 0246 — — — ...
Page 129
... AN13 1110 AN14 1111 AN15 V AN1 © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The ADC module has six 16-bit registers: • ADC Control Register 1 (ADCON1) • ADC Control Register 2 (ADCON2) • ADC Control Register 3 (ADCON3) • ADC Input Select Register (ADCHS) • ADC Port Configuration Register (ADPCFG) • ...
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... The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. © 2008 Microchip Technology Inc. number of ...
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... There are 64 possible options for T EQUATION 19-1: ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V “ ...
Page 132
... REF circuit. DS70116H-page 132 R Max V Temperature DD s 2.5 kΩ 4.5V to 5.5V -40°C to +85°C 2.5 kΩ 3.0V to 5.5V -40°C to +125°C Channels Configuration REF REF CH X ANx S/H ADC REF REF ANx S/H ADC ANx REF © 2008 Microchip Technology Inc. ...
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... The following figure depicts the recommended circuit for the conversion rates above 100 ksps. The dsPIC30F5013 is shown as an example. FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC 0.1 μF 0.01 μF 10 The configuration procedures below give the required setup values for the conversion speeds above 100 ksps ...
Page 134
... ≤ 250Ω Sampling Switch leakage V = 0.6V T ± 500 nA PIN AD CONV AD . The combined impedance HOLD , is 2.5 kΩ. After the S ≤ 3 kΩ HOLD = DAC capacitance = negligible if Rs ≤ 2.5 kΩ. © 2008 Microchip Technology Inc. ...
Page 135
... ADCBUF register. If the ADC interrupt is enabled, the device wakes up from Sleep. If the ADC interrupt is not enabled, the ADC module is turned off, although the ADON bit remains set. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 19.10.2 A/D OPERATION DURING CPU IDLE MODE The ADSIDL bit selects if the module stops on Idle or continues on Idle ...
Page 136
... Any external components connected (via high impedance analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin and V as ESD DD SS and the input voltage exceeds this SS © 2008 Microchip Technology Inc. ...
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TABLE 19-2: A/D CONVERTER REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — ...
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... NOTES: DS70116H-page 138 © 2008 Microchip Technology Inc. ...
Page 139
... In Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following features: • ...
Page 140
... RC oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70116H-page 140 Description (1) . (2) . (1) . (1) . (1) . (3) /4 output . OSC (3) . © 2008 Microchip Technology Inc. ...
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... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2008 Microchip Technology Inc. dsPIC30F5011/5013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock ...
Page 142
... COSC<1:0> (LP selected as main oscillator) and OSC2 FPR1 FPR0 Function CLKO CLKO OSC2 0 0 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 OSC2 1 0 — — (Notes 1, 2) (Notes — — (Notes 1, 2) © 2008 Microchip Technology Inc. ...
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... PLL multiplier (respectively) is applied. Note: When a 16x PLL is used, the FRC frequency must not be tuned to a frequency greater than 7.5 MHz. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 TABLE 20-4: TUN<3:0> Bits 0111 0110 ...
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... To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: Byte Write “0x78” to OSCCON high Byte Write “0x9A” to OSCCON high Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2008 Microchip Technology Inc. ...
Page 145
... POR timer and place the device in the Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up since this is viewed as the resump- tion of normal operation ...
Page 146
... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70116H-page 146 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE CASE 2 DD © 2008 Microchip Technology Inc. ...
Page 147
... A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source based on the device Configuration bit values (FOS<1:0> and © 2008 Microchip Technology Inc. dsPIC30F5011/5013 FPR<3:0>). Furthermore Oscillator mode is selected, the BOR will activate the Oscillator Start-up Timer (OST) ...
Page 148
... Legend unchanged unknown unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70116H-page 148 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( © 2008 Microchip Technology Inc. ...
Page 149
... Illegal Operation Reset 0x000000 Legend unchanged unknown unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ...
Page 150
... T . PWRT delay and OST POR timer delay are not applied. In order to have the small- est possible start-up delay when waking up from Sleep, one of these faster wake-up options should be selected before entering Sleep. © 2008 Microchip Technology Inc. delays PWRT ...
Page 151
... RCON register is set upon wake-up. Any Reset other than POR will set the Idle Status bit POR, the Idle bit is cleared. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 If Watchdog Timer is enabled, then the processor will wake-up from Idle mode upon WDT time-out. The Idle and WDTO status bits are both set ...
Page 152
... PGD and PGC pin functions in all dsPIC30F devices EMUD1/EMUC1, EMUD2/EMUC2 EMUD3/EMUC3 is selected as the Debug I/O pin pair, then a 7-pin interface is required, as the EMUDx/EMUCx pin functions ( are not multiplexed with the PGD and PGC pin functions. © 2008 Microchip Technology Inc. EMUD/EMUC, and , ...
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TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 TUN3 TUN2 COSC<1:0> TUN1 PMD1 0770 T5MD T4MD T3MD T2MD T1MD PMD2 0772 ...
Page 154
... NOTES: DS70116H-page 154 © 2008 Microchip Technology Inc. ...
Page 155
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Most bit-oriented rotate/shift instructions) have two operands: • ...
Page 156
... Moreover, double word moves require two cycles. The double word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157). indirect writes, and Description © 2008 Microchip Technology Inc. ...
Page 157
... Y data space prefetch address register for DSP instructions ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Description DS70116H-page 157 ...
Page 158
... Branch if Accumulator A overflow Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> © 2008 Microchip Technology Inc Status Flags Cycles Affected 1 1 OA,OB,SA, C,DC,N,OV,Z 1 ...
Page 159
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2008 Microchip Technology Inc. dsPIC30F5011/5013 # of Description Words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 160
... Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W(ns+ Move Double from Ws to W(nd+1):W(nd) Prefetch and store accumulator © 2008 Microchip Technology Inc Status Flags Cycles Affected 1 18 N,Z,C,OV 1 ...
Page 161
... RRC Ws,Wd 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd © 2008 Microchip Technology Inc. dsPIC30F5011/5013 # of Description Words Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 162
... Wn = byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws © 2008 Microchip Technology Inc Status Flags Cycles Affected 1 1 None 1 1 None 1 ...
Page 163
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. dsPIC30F5011/5013 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market ...
Page 164
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool PC-hosted environment by ® DSCs on an © 2008 Microchip Technology Inc. ...
Page 165
... MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 22.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 166
... ICs, CAN, IrDA EE OQ ® battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. © 2008 Microchip Technology Inc. kits and ® , PowerSmart ...
Page 167
... TABLE 23-1: OPERATING MIPS VS. VOLTAGE V Range Temp Range DD 4.75-5.5V -40°C to 85°C 4.75-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C © 2008 Microchip Technology Inc. dsPIC30F5011/5013 (1) (except V and MCLR) ............................................... -0. ....................................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ................................................................................................... ± (2) ..............................................................................................................200 mA pin, inducing currents greater than 80 mA, may cause latchup ...
Page 168
... INT I O θ Typ Max Unit Notes 39 — °C — °C/W 1 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V/ms 0-5V in 0.1 sec 0- © 2008 Microchip Technology Inc. ...
Page 169
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory DD are operational. No peripheral modules are operating. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 170
... FRC (~2MIPS) LPRC (~512 kHz) 4 MIPS EC mode, 4X PLL 10 MIPS EC mode, 4X PLL 20 MIPS EC mode, 8X PLL 30 MIPS EC mode,16X PLL © 2008 Microchip Technology Inc. ...
Page 171
... LVD, BOR, WDT, etc. are all switched off. The Δ current is the additional current consumed when the module is enabled. This current should be 3: added to the base I current. PD © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...
Page 172
... Units Conditions bus disabled bus enabled bus disabled V SM bus enabled μ 5V PIN SS μA ≤ V ≤ PIN DD Pin at high-impedance μA ≤ V ≤ PIN DD Pin at high-impedance μA ≤ V ≤ PIN DD μA ≤ V ≤ XT PIN DD and LP Osc mode © 2008 Microchip Technology Inc. ...
Page 173
... These parameters are characterized but not tested in manufacturing. FIGURE 23-1: LOW-VOLTAGE DETECT CHARACTERISTICS V DD LV10 LVDIF (LVDIF set by hardware) © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min ...
Page 174
... V — — V — — V — 2.65 V — 2.86 V — 2.97 V — 3.18 V — 3.50 V — 3.71 V — 3.82 V — 4.03 V — 4.24 V — 4.45 V — 4.77 V — — V (Device not in Brown-out Reset) Power-Up Time-out © 2008 Microchip Technology Inc. ...
Page 175
... During Programming EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 176
... DC Spec Section 23.1 “DC DD Characteristics”. Load Condition 2 – for OSC2 Pin 464 Ω for all pins except OSC2 OS20 OS30 OS30 OS25 OS40 ≤ +85°C for Industrial A ≤ +125°C for Extended OS31 OS31 OS41 © 2008 Microchip Technology Inc. ...
Page 177
... Measurements are taken ERC modes. The CLKOUT signal is measured on the OSC2 pin. CLKOUT is low for the Q1-Q2 period (1/2 T © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 178
... V = 4 ≤ +85° 3 ≤ +125° 3 ≤ +85° 4 ≤ +125° 4 ≤ +85° 3 ≤ +85° 4 ≤ +125° 4 © 2008 Microchip Technology Inc. ...
Page 179
... Frequency calibrated at 7.372 MHz, 25°C and 5V. TUN bits can be used to compensate for temperature drift. TABLE 23-19: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65A OS65B OS65C Note 1: Change of LPRC frequency as V © 2008 Microchip Technology Inc. dsPIC30F5011/5013 (3) T MIPS MIPS CY (1) (2) (μsec) w/o PLL w PLL x4 20.0 0.05 1.0 1 ...
Page 180
... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended A (1)(2)(3) (4) Min Typ Max — — — — — — CY Units Conditions OSC © 2008 Microchip Technology Inc. ...
Page 181
... TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 SY10 SY20 SY13 SY13 DS70116H-page 181 ...
Page 182
... Extended A Units Conditions μs -40°C to +85°C ms -40°C to +85° User programmable μs -40°C to +85°C μ 2. 3.3V, ±10 5V, ±10% DD μs ≤ (D034) DD BOR — OSC1 period OSC μs -40°C to +85°C © 2008 Microchip Technology Inc. ...
Page 183
... Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 SY40 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 184
... Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TA15 — ns — ns — ns Must also meet parameter TA15 — ns — ns — ns — — prescale value (1, 8, 64, 256) — kHz 1.5 T — CY © 2008 Microchip Technology Inc. ...
Page 185
... TxCK Input Period Synchronous, TC20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer3 and Timer5 are Type C. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min ...
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... T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended A (1) Min No Prescaler 0 With Prescaler 10 No Prescaler 0 With Prescaler 40)/N CY Max Units Conditions — ns — ns — ns — ns — prescale value (1, 4, 16) © 2008 Microchip Technology Inc. ...
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... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 OC10 OC11 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
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... OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min Typ Max Units — — — — ns -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Conditions © 2008 Microchip Technology Inc. ...
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... CSCK (SCKE = 0) CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 CS20 CS21 ...
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... CY 20 (3) 30 — — (4) — (4) — (4) — (4) — — — — — — 20 — — — — — — 20 — — ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions Note 1 ns Note © 2008 Microchip Technology Inc. ...
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... These parameters are characterized but not tested in manufacturing. 2: These values assume BIT_CLK frequency is 12.288 MHz. 3: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 CS62 CS21 CS71 CS72 ...
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... Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — ns — ns See parameter DO32 — ns See parameter DO31 — ns See parameter DO32 — ns See parameter DO31 30 ns — ns — ns © 2008 Microchip Technology Inc. ...
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... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 SP10 SP21 SP35 SP20 LSb ...
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... SP52 LSb SP51 LSb IN -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions — ns — — ns See Parameter DO32 — ns See Parameter DO31 30 ns — ns — ns — — ns © 2008 Microchip Technology Inc. ...
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... SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 SP70 SP73 SP35 SP72 SP52 BIT14 - - - - - -1 LSb SP30,SP31 BIT14 - - - -1 LSb IN SP52 SP72 SP73 SP51 DS70116H-page 195 ...
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... X CY — — -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — — ns See parameter DO32 — ns See parameter DO31 30 ns — ns — ns — — © 2008 Microchip Technology Inc. ...
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... FIGURE 23-19: I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 ...
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... C pins (for 1 MHz mode only). © 2008 Microchip Technology Inc. ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions C is specified from 10 to 400 specified from 10 to 400 pF Only relevant for ...
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... SDA Start Condition 2 FIGURE 23-21: I C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out © 2008 Microchip Technology Inc. dsPIC30F5011/5013 IS33 IS11 IS10 IS26 IS25 IS40 IS34 Stop Condition IS21 IS33 IS45 DS70116H-page 199 ...
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... Only relevant for repeated Start condition μs μs μs After this period the first clock pulse is generated μs μs μs μs μ μs Time the bus must be free before a new transmission μs can start μs pF © 2008 Microchip Technology Inc. ...