DSPIC30F5013-20I/PT Microchip Technology, DSPIC30F5013-20I/PT Datasheet - Page 58

• Manufacturer Part Number: DSPIC30F5013-20I/PT
• Description: IC DSPIC MCU/DSP 66K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F501320IPT

dsPIC30F5011/5013
7.3.2
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
program the block.
EXAMPLE 7-5:
DS70116H-page 58
MOV
MOV
MOV
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
WRITING A BLOCK OF DATA
EEPROM
#5
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1
#data1,W2
W2
#data2,W2
W2
#data3,W2
W2
#data4,W2
W2
#data5,W2
W2
#data6,W2
W2
#data7,W2
W2
#data8,W2
W2
#data9,W2
W2
#data10,W2
W2
#data11,W2
W2
#data12,W2
W2
#data13,W2
W2
#data14,W2
W2
#data15,W2
W2
#data16,W2
W2
#0x400A,W0
W0
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
DATA EEPROM BLOCK WRITE
TBLPAG
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
[ W0]++
NVMCON
NVMKEY
NVMKEY
; Init pointer
; Get 1st data
; write data
; Get 2nd data
; write data
; Get 3rd data
; write data
; Get 4th data
; write data
; Get 5th data
; write data
; Get 6th data
; write data
; Get 7th data
; write data
; Get 8th data
; write data
; Get 9th data
; write data
; Get 10th data
; write data
; Get 11th data
; write data
; Get 12th data
; write data
; Get 13th data
; write data
; Get 14th data
; write data
; Get 15th data
; write data
; Get 16th data
; write data. The NVMADR captures last table access address.
; Select data EEPROM for multi word op
; Operate Key to allow program operation
; Block all interrupts with priority <7 for
; next 5 instructions
; Write the 0x55 key
; Write the 0xAA key
; Start write cycle
© 2008 Microchip Technology Inc.