PIC18F4680-I/ML Microchip Technology, PIC18F4680-I/ML Datasheet - Page 215

• Manufacturer Part Number: PIC18F4680-I/ML
• Description: IC MCU FLASH 32KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4680-I/ML

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3328Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11 bit
• Package: 44QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4680 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

17.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
FIGURE 17-17:
TABLE 17-3:
© 2007 Microchip Technology Inc.
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE
F
CY
2
C™ interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
2
C Master mode, the BRG is
SCL
SSPM3:SSPM0
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
F
CY
CY
PIC18F2585/2680/4585/4680
*2
) on the
Reload
Control
Preliminary
CLKO
Reload
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
BRG Down Counter
2
C specification (which applies to rates greater than
SSPADD<6:0>
BRG Value
0Dh
0Ah
0Ah
19h
20h
64h
28h
03h
00h
F
OSC
(2 Rollovers of BRG)
/4
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
DS39625C-page 213
100 kHz
308 kHz
100 kHz
100 kHz
F
SCL
(1)
(1)
(1)
(1)