PIC18F6621-I/PT Microchip Technology, PIC18F6621-I/PT Datasheet - Page 9

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6621-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 53
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.75KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Details

3.1.1
When using low voltage ICSP, the part must be sup-
plied by the voltage specified in parameter #D111 if a
bulk erase is to be executed. All other bulk erase details
as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the bulk erase
limit, refer to the erase methodology described in
Sections 3.1.2 and 3.2.2.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the bulk erase
limit, follow the methodology described in Section 3.3
and write ‘1’s to the array.
 2003 Microchip Technology Inc.
LOW VOLTAGE ICSP BULK ERASE
3.1.2
Regardless of whether high or low voltage ICSP is used,
it is possible to erase a single row (64 bytes of data) in
all panels at once. For example, in the case of a
64-Kbyte device (8 panels), 512 bytes through 64 bytes
in each panel can be erased simultaneously during each
erase sequence. In this case, the offset of the erase
within each panel is the same (see Figure 3-5). Multi-
panel single row erase is enabled by appropriately con-
figuring the Programming Control register located at
3C0006h.
The multi-panel single row erase duration is externally
timed and is controlled by PGC. After a “Start Program-
ming” command is issued (4-bit command, ‘1111’), a
NOP is issued, where the 4th PGC is held high for the
duration of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time spec-
ified by parameter P10 to allow high voltage discharge
of the memory array.
The code sequence to erase a PIC18F6X2X/8X2X
device is shown in Table 3-3. The flow chart shown in
Figure 3-3 depicts the logic necessary to completely
erase a PIC18F6X2X/8X2X device. The timing dia-
gram that details the “Start Programming” command,
and parameters P9 and P10 is shown in Figure 3-6.
Note:
PIC18F6X2X/8X2X
ICSP MULTI-PANEL SINGLE ROW
ERASE
The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
DS30499B-page 9