PIC18F8620-I/PT Microchip Technology, PIC18F8620-I/PT Datasheet - Page 283

• Manufacturer Part Number: PIC18F8620-I/PT
• Description: IC MCU FLASH 32KX16 EE 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8620-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 68
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.75KB
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Details

INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
CNT
If CNT
PC
If CNT
PC
No
No
No
Q1
Q1
Q1
PIC18F6520/8520/6620/8620/6720/8720
=
=
=
=
=
register ‘f’
operation
operation
operation
Increment f, skip if 0
[ label ]
0
d
a
(f) + 1
skip if result = 0
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0011
No
No
No
Q2
Q2
Q2
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
f
[0,1]
[0,1]
by a 2-word instruction.
255
dest,
INCFSZ
:
:
INCFSZ
11da
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
ffff
f [,d [,a]
CNT, 1, 0
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
REG
If REG
PC
If REG
PC
Q1
Q1
Q1
=
=
=
=
=
register ‘f’
operation
operation
operation
Increment f, skip if not 0
[ label ]
0
d
a
(f) + 1
skip if result
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
f
[0,1]
[0,1]
255
by a 2-word instruction.
dest,
INFSNZ
INFSNZ
10da
operation
operation
operation
Process
Data
0
No
No
No
Q3
Q3
Q3
DS39609B-page 281
REG, 1, 0
ffff
f [,d [,a]
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff