PIC18F6720-I/PT Microchip Technology, PIC18F6720-I/PT Datasheet - Page 206
![IC MCU FLASH 64KX16 EE 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6720-I/PT
Manufacturer Part Number
PIC18F6720-I/PT
Description
IC MCU FLASH 64KX16 EE 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F8520T-IPT.pdf
(380 pages)
3.PIC18F8520T-IPT.pdf
(40 pages)
4.PIC18F6620-IPT.pdf
(14 pages)
5.PIC18F6620-IPT.pdf
(12 pages)
Specifications of PIC18F6720-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.75 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
52
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
25 MHz
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6720-I/PT
Manufacturer:
TI
Quantity:
4 390
Company:
Part Number:
PIC18F6720-I/PT
Manufacturer:
MICROCHIP
Quantity:
40
Company:
Part Number:
PIC18F6720-I/PT
Manufacturer:
MICROCHIP
Quantity:
13
Company:
Part Number:
PIC18F6720-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F6720-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC18F6720-I/PT(C01)
Manufacturer:
MIC
Quantity:
20 000
PIC18F6520/8520/6620/8620/6720/8720
18.2
In this mode, the USARTs use standard Non-Return-to-
Zero (NRZ) format (one Start bit, eight or nine data bits
and one Stop bit). The most common data format is
8 bits. An on-chip dedicated 8-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The Baud Rate Generator produces a
clock, either 16 or 64 times the bit shift rate, depending
on bit BRGH (TXSTAx<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTAx<4>).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
18.2.1
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREGx register (if available).
Once the TXREGx register transfers the data to the
TSR register (occurs in one T
is empty and flag bit, TXx1IF (PIR1<4> for USART1,
FIGURE 18-1:
DS39609B-page 204
USART Asynchronous Mode
USART ASYNCHRONOUS
TRANSMITTER
TXIE
Interrupt
USART TRANSMIT BLOCK DIAGRAM
TXIF
TXEN
Baud Rate Generator
CY
SPBRG
), the TXREGx register
Baud Rate CLK
MSb
(8)
TX9D
TXREG Register
TSR Register
TX9
8
Data Bus
interrupt logic is tied to this bit, so the user has to poll this
PIR3<4> for USART2), is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXxIE
(PIE1<4> for USART1, PIE<4> for USART2). Flag bit
TXxIF will be set, regardless of the state of enable bit
TXxIE and cannot be cleared in software. It will reset
only when new data is loaded into the TXREGx register.
While flag bit TXIF indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. Status bit TRMT is a read-only
bit, which is set when the TSR register is empty. No
bit in order to determine if the TSR register is empty.
To set up an Asynchronous Transmission:
1.
2.
3.
4.
5.
6.
7.
Note:
Note 1: The TSR register is not mapped in data
Initialize the SPBRGx register for the appropri-
ate baud rate. If a high-speed baud rate is
desired, set bit BRGH (Section 18.1 “USART
Baud Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXxIE in
the appropriate PIE register.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN,
which will also set bit TXxIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREGx register (starts
transmission).
LSb
2: Flag bit TXIF is set when enable bit TXEN
0
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
memory, so it is not available to the user.
is set.
TRMT
and Control
Pin Buffer
2004 Microchip Technology Inc.
SPEN
TX pin