PIC18F6720-I/PT Microchip Technology, PIC18F6720-I/PT Datasheet - Page 255

IC MCU FLASH 64KX16 EE 64TQFP

PIC18F6720-I/PT

Manufacturer Part Number
PIC18F6720-I/PT
Description
IC MCU FLASH 64KX16 EE 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F6720-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.75 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
52
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
25 MHz
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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FIGURE 23-2:
23.4
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro
divided on binary boundaries into individual blocks,
each of which has three separate code protection bits
associated with it:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
The code protection bits are located in Configuration
Registers 5L through 7H. Their locations within the
registers are summarized in Table 23-3.
TABLE 23-3:
 2004 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
Note 1:
(INTCON<1>)
(INTCON<7>)
Note
INSTRUCTION FLOW
Instruction
Instruction
Executed
INTF flag
GIEH bit
CLKO
Fetched
INT pin
OSC1
File Name
Program Verification and
Code Protection
1:
2:
3:
4:
®
PC
(4)
Unimplemented in PIC18FX520 and PIC18FX620 devices.
devices. The user program memory is
XT, HS or LP Oscillator mode assumed.
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
T
CLKO is not available in these oscillator modes, but shown here for timing reference.
OST
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L EBTR7
CONFIG7H
Inst(PC) = Sleep
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC - 1)
= 1024 T
PIC18F6520/8520/6620/8620/6720/8720
SUMMARY OF CODE PROTECTION REGISTERS
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
(drawing not to scale). This delay will not occur for RC and EC Oscillator modes.
WRT7
CP7
WRTD
Bit 7
CPD
Inst(PC + 2)
Sleep
PC+2
(1)
(1)
(1)
EBTR6
WRT6
EBTRB
CP6
WRTB
Bit 6
CPB
Processor in
(1)
Sleep
(1)
(1)
PC+4
EBTR5
WRT5
CP5
WRTC
Bit 5
T
OST
(1)
(2)
(1)
(1)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
EBTR4
Inst(PC + 4)
Inst(PC + 2)
WRT4
CP4
In the PIC18FXX20 family, the block size varies with
the size of the user program memory. For PIC18FX520
devices, program memory is divided into four blocks of
8 Kbytes each. The first block is further divided into a
boot block of 2 Kbytes and a second block (Block 0) of
6 Kbytes, for a total of five blocks. The organization of
the blocks and their associated code protection bits are
shown in Figure 23-3.
For PIC18FX620 and PIC18FX720 devices, program
memory is divided into blocks of 16 Kbytes. The first
block is further divided into a boot block of 512 bytes
and a second block (Block 0) of 15.5 Kbytes, for a total
of nine blocks. This produces five blocks for 64-Kbyte
devices and nine for 128-Kbyte devices. The organiza-
tion of the blocks and their associated code protection
bits are shown in Figure 23-4.
Bit 4
PC+4
(1)
(1)
(1)
Interrupt Latency
EBTR3
WRT3
Dummy Cycle
Bit 3
CP3
PC + 4
(1,2)
EBTR2
WRT2
Bit 2
CP2
(3)
Dummy Cycle
Inst(0008h)
0008h
EBTR1
WRT1
Bit 1
CP1
DS39609B-page 253
Inst(000Ah)
Inst(0008h)
000Ah
EBTR0
WRT0
Bit 0
CP0

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