AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1022

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

• DST_DSCR
0: Destination address is updated when the descriptor is fetched from the memory.
1: Buffer Descriptor Fetch operation is disabled for the destination.
• FC
This field defines which device controls the size of the buffer transfer, also referred as to the Flow Controller.
• SRC_INCR
• DST_INCR
• IEN
If this bit is cleared, when the buffer transfer is completed, the BTC[x] flag is set in the EBCISR status register. This bit is
active low.
• AUTO
Automatic multiple buffer transfer is enabled. When set, this bit enables replay mode or contiguous mode when several buf-
fers are transferred.
6438F–ATARM–21-Jun-10
SRC_INCR
DST_INCR
000
001
010
011
100
101
110
111
FC
00
01
10
00
01
10
Type of addressing scheme
Peripheral-to-Peripheral
Peripheral-to-Peripheral
Peripheral-to-Peripheral
Type of addressing mode
Memory-to-Peripheral
Peripheral-to-Memory
Peripheral-to-Memory
Memory-to-Peripheral
Memory-to-Memory
DECREMENTING
INCREMENTING
DECREMENTING
Type of transfer
INCREMENTING
FIXED
FIXED
Destination Peripheral
Source Peripheral
DMA Controller
DMA Controller
DMA Controller
DMA Controller
Flow Controller
Peripheral
Peripheral
AT91SAM9G45
1022