AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 249
AT91SAM9G45-CU
Manufacturer Part Number
AT91SAM9G45-CU
Description
MCU ARM9 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-CU.pdf
(10 pages)
Specifications of AT91SAM9G45-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
800 MHz
Number Of Programmable I/os
160
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Figure 22-21. Automatic Update During AUTO-REFRESH Command and SDRAM Access
22.4.4.2
6438F–ATARM–21-Jun-10
COMMAND
SDCLK
BA[1:0]
A[12:0]
CKE
Power-down Mode
NOP
PRCHALL
0
This mode is activated by setting the low-power command bits [LPCB] to ‘10’.
Power-down mode is used when no access to the SDRAM device is possible. In this mode,
power consumption is greater than in self refresh mode. This state is similar to normal mode (No
low-power mode/No self refresh mode), but the CKE pin is low and the input and output buffers
are deactivated as soon the SDRAM device is no longer accessible. In contrast to self refresh
mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64
ms). As no auto-refresh operations are performed in this mode, the DDRSDRC carries out the
refresh operation. In order to exit low-power mode, a NOP command is required in the case of
Low-power SDR-SDRAM and SDR-SDRAM devices. In the case of Low-power DDR-SDRAM
devices, the controller generates a NOP command during a delay of at least TXP. In addition,
Low-power DDR-SDRAM and DDR2-SDRAM must remain in power-down mode for a minimum
period of TCKE periods.
The exit procedure is faster than in self refresh mode. See
DDRSDRC returns to power-down mode as soon as the SDRAM device is not selected. It is
possible to define when power-down mode is enabled by setting the register LPR, timeout com-
mand bit.
• 00 = Power-down mode is enabled as soon as the SDRAM device is not selected
• 01 = Power-down mode is enabled 64 clock cycles after completion of the last access
• 10 = Power-down mode is enabled 128 clock cycles after completion of the last access
Trp
NOP
ARFSH
2
Trfc
NOP
Pasr-Tcr-Ds
MRS
Update Extended mode
register
Tmrd
NOP
Figure 22-22 on page
ACT
0
AT91SAM9G45
250. The
249
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