AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1169
AT91SAM9G45-CU
Manufacturer Part Number
AT91SAM9G45-CU
Description
MCU ARM9 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-CU.pdf
(10 pages)
Specifications of AT91SAM9G45-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
800 MHz
Number Of Programmable I/os
160
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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Quantity:
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Manufacturer:
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46.12 Core Power Supply POR Characteristics
Table 46-25. Power-On-Reset Characteristics
46.12.1
46.12.2
6438F–ATARM–21-Jun-10
Symbol
V
V
T
th+
th-
RES
Power Sequence Requirements
Power-Up Sequence
Parameter
Threshold Voltage Rising
Threshold Voltage Falling
Reset Time
The AT91SAM9G45 board design must comply with the power-up guidelines below to guaran-
tee reliable operation of the device. Any deviation from these sequences may prevent the device
from booting.
Figure 46-2.
VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that
these power sources reach their target values prior to the release of POR.
• VDDIOP must be
• VDDIOM must reach V
(Tres + T1) after VDDCORE has reached
(Tres +T1 +T2) after VDDCORE has reached
– T
– T1 = 3 x T
– T2 = 16 x T
RES
VDDCOREtyp
Core Supply POR Output
is a POR characteristic
VDDIOtyp
VDD (V)
Conditions
Minimum Slope of +2.0V/30ms
VDDCORE and VDDIO Constraints at Startup
SLCK
Vth+
Voh
Vih
SLCK
SLCK
V
IH
OH
(refer to DC characteristics,
(refer to DC characteristics,
<--- Tres --->
V
th+
.
V
Min
0.5
0.4
30
th+
< T1 >
Table
<------------ T2----------->
Table
46-2, for more details) within
Typ
0.7
0.6
70
46-2, for more details) within
AT91SAM9G45
VDDIO > Vih
VDDIO > Voh
Max
0.89
0.85
130
VDDCORE
VDDIO
t
Units
μs
V
V
1169
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