DSPIC30F6010-30I/PF Microchip Technology, DSPIC30F6010-30I/PF Datasheet - Page 2

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DSPIC30F6010-30I/PF

Manufacturer Part Number
DSPIC30F6010-30I/PF
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F6010-30I/PF

Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
144KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F601030IPF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F6010-30I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6010-30I/PF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F6010
TABLE 2:
DS80459D-page 2
Operations
Note 1:
EEPROM
Controller
Compare
Compare
Interrupt
Module
Timers
Output
Output
PWM
Data
CPU
CPU
CPU
CPU
CPU
CPU
CPU
ADC
ADC
PSV
QEI
Only those issues indicated in the last column apply to the current silicon revision.
Unsigned MAC
Y Data Space
Modification
32-bit Mode
PWM Mode
Index Pulse
Instructions
Sequential
Time Base
MAC Class
Instruction
Nested DO
Instruction
Instruction
Gain Error
Sampling
Prescaler
SILICON ISSUE SUMMARY
Feature
Address
REPEAT
with ±4
DAW.b
I/O Pin
Speed
Loops
Traps
DISI
Number
Item
10.
12.
13.
14.
15.
16.
17.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Data EEPROM is operational up to 20 MIPS.
The Unsigned Integer mode for the MAC-type DSP instructions
does not function as specified.
Sequential MAC instructions, which prefetch data from Y data
space using ±4 address modification, will cause an address
error trap.
The Decimal Adjust instruction, DAW.b, may improperly clear
the Carry bit, C (SR<0>).
In certain instructions, fetching one of the operands from
program memory using Program Space Visibility (PSV) will
corrupt specific bits in the STATUS Register, SR.
When using two DO loops in a nested fashion, terminating the
inner-level DO loop by setting the EDT bit (CORCON<11>) will
produce unexpected results.
When an instruction that writes to a location in the address
range of Y data memory is immediately followed by a MAC-type
DSP instruction that reads a location also resident in Y data
memory, the operations will not be performed as specified.
When a catastrophic overflow of any of the accumulators
causes an arithmetic (math) error trap, the overflow Status bits
need to be cleared to exit the trap handler.
When a REPEAT loop is interrupted by two or more interrupts in
a nested fashion, an address error trap may be caused.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
The 32-bit general purpose timers do not function as specified
for prescaler ratios other than 1:1.
Output compare will produce a glitch when loading 0% duty
cycle in PWM mode. It will also miss the next compare after the
glitch.
The Output Compare module will produce a glitch on the output
when an I/O pin is initially set high, and the module is
configured to drive the pin low at a specified time.
The Reset on Index Pulse mode does not work.
Sampling multiple channels sequentially using any conversion
trigger other than the auto-convert feature requires SAMC bits
to be non-zero.
The 10-bit ADC exhibits a maximum gain error of ±3 Least
Significant bits (LSbs).
The Motor Control PWM time base prescaler options, 1:4, 1:16
and 1:64, may produce unexpected results when used to
generate PWM pulses.
Issue Summary
© 2010 Microchip Technology Inc.
Revisions
B1
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)

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