P87C660X2BBD,157 NXP Semiconductors, P87C660X2BBD,157 Datasheet - Page 88

IC 80C51 MCU 16K OTP 44-LQFP

P87C660X2BBD,157

Manufacturer Part Number
P87C660X2BBD,157
Description
IC 80C51 MCU 16K OTP 44-LQFP
Manufacturer
NXP Semiconductors
Series
87Cr
Datasheet

Specifications of P87C660X2BBD,157

Core Processor
8051
Core Size
8-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LQFP
Processor Series
P87C6x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, UART
Maximum Clock Frequency
16 MHz, 33 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
568-3204
935273061157
P87C660X2BBD

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
P87C660X2BBD,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level HIGH
I – Instruction (program memory contents)
L – Logic level LOW, or ALE
2003 Oct 02
PORT 0
PORT 2
80C51 8-bit microcontroller family
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
PSEN
ALE
RD
PORT 0
PORT 2
PSEN
ALE
t
AVLL
2
C interfaces
FROM RI OR DPL
A0–A7
t
LLAX
t
t
AVWL
LHLL
t
t
LLWL
AVLL
A0–A7
Figure 50. External Program Memory Read Cycle
16 KB OTP/ROM, 512B
t
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPF
RLAZ
Figure 51. External Data Memory Read Cycle
t
LLDV
t
t
t
AVIV
LLAX
LLPL
t
LLIV
t
t
PLIV
RLDV
A0–A15
t
PLAZ
t
PLPH
t
RLRH
t
PXIX
INSTR IN
88
t
RHDX
DATA IN
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
Examples: t
t
PXIZ
t
RHDZ
t
t
AVLL
WHLH
LLPL
= Time for address valid to ALE LOW.
=Time for ALE LOW to PSEN LOW.
A0–A7
A0–A7 FROM PCL
A0–A15 FROM PCH
P8xC660X2/661X2
A8–A15
SU00006
INSTR IN
Product data
SU00025

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