ADUC834BSZ Analog Devices Inc, ADUC834BSZ Datasheet - Page 50

• Manufacturer Part Number: ADUC834BSZ
• Description: IC ADC DUAL16/24BIT W/MCU 52MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC834BSZ

• Core Size: 8-Bit
• Program Memory Size: 62KB (62K x 8)
• Oscillator Type: Internal
• Core Processor: 8052
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 3x16b, 4x24b; D/A 1x12b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Controller Family/series: (8052) ADUC
• No. Of I/o's: 26
• Eeprom Memory Size: 62KB
• Ram Memory Size: 2KB
• Cpu Speed: 12.58MHz
• Package: 52MQFP
• Device Core: 8052
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Interface Type: I2C/SPI/UART
• On-chip Adc: 4-chx16-bit|4-chx24-bit
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC834
P1.2 to P1.7
The remaining Port 1 pins (P1.2–P1.7) can only be configured as
analog input (ADC) or digital input pins. By (power-on) default,
these pins are configured as analog inputs, i.e., ‘1’ written in the
corresponding Port 1 register bit. To configure any of these pins
as digital inputs, the user should write a ‘0’ to these port bits to
configure the corresponding pin as a high impedance digital
input. Figure 39 illustrates this function. Note that there are no
output drivers for Port 1 pins, and they therefore cannot be
used as outputs.
Port 2
Port 2 is a bidirectional port with internal pull-up resistors directly
controlled via the P2 SFR. Port 2 also emits the high order
address bytes during fetches from external program memory
and middle and high order address bytes during accesses to the
24-bit external data memory space.
As shown in Figure 40, the output drivers of Ports 2 are switch-
able to an internal ADDR bus by an internal CONTROL signal
for use in external memory accesses (as for Port 0). In external
memory addressing mode (CONTROL = 1), the port pins
feature push/pull operation controlled by the internal address
bus (ADDR line). However unlike the P0 SFR during external
memory accesses, the P2 SFR remains unchanged.
In general-purpose I/O port mode, Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups (Figure 38) and,
in that state, they can be used as inputs. As inputs, Port 2 pins
being pulled externally low will source current because of the
internal pull-up resistors. Port 2 pins with 0s written to them
will drive a logic low output voltage (V
of sinking 1.6 mA.
Port 3
Port 3 is a bidirectional port with internal pull-ups directly
controlled via the P3 SFR.
Port 3 pins that have 1s written to them are pulled high by the
internal pull-ups and in that state they can be used as inputs. As
inputs, Port 3 pins being pulled externally low will source current
because of the internal pull-ups. Port 3 pins with 0s written to
them will drive a logic low output voltage (V
capable of sinking 1.6 mA.
TO LATCH
INTERNAL
LATCH
Figure 39. P1.2 to P1.7 Bit Latch and I/O Buffer
WRITE
READ
READ
BUS
PIN
Figure 40. Port 2 Bit Latch and I/O Buffer
INTERNAL
TO LATCH
LATCH
WRITE
READ
READ
BUS
PIN
LATCH
D
CL
Q
Q
TO ADC
LATCH
D
CL
ADDR
*SEE FIGURE 38 FOR
DETAILS OF INTERNAL PULL-UP
Q
Q
CONTROL
OL
) and will be capable
OL
DV
DD
) and will be
DV
P1.x
PIN
DD
INTERNAL
PULL-UP*
P2.x
PIN
–50–
Port 3 pins also have various secondary functions described in
Table XXV. The alternate functions of Port 3 pins can only be
activated if the corresponding bit latch in the P3 SFR contains a 1.
Otherwise, the port pin is stuck at 0.
Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 3 pins have the same bit latch and I/O buffer configurations
as the P1.0 and P1.1 as shown in Figure 41. The internal pull-up
configuration is also defined by that in Figure 38.
Additional Digital I/O
In addition to the port pins, the dedicated SPI/I
and SDATA/MOSI) also feature both input and output functions.
Their equivalent I/O architectures are illustrated in Figure 42
and Figure 44, respectively, for SPI operation and in Figure 43
and Figure 45 for I
Notice that in I
(Q1) is disabled leaving only a weak pull-up (Q2) present. By
contrast, in SPI mode (SPE = 1), the strong pull-up FET (Q1)
is controlled directly by SPI hardware, giving the pin push/pull
capability.
In I
operate in parallel in order to provide an extra 60% or 70% of
current sinking capability. In SPI mode, however, (SPE = 1), only
one of the pull-down FETs (Q3) operates on each pin resulting
in sink capabilities identical to that of Port 0 and Port 2 pins.
On the input path of SCLOCK, notice that a Schmitt trigger
conditions the signal going to the SPI hardware to prevent false
triggers (double triggers) on slow incoming edges. For incoming
signals from the SCLOCK and SDATA pins going to I
ware, a filter conditions the signals in order to reject glitches of
up to 50 ns in duration.
2
INTERNAL
TO LATCH
C mode (SPE = 0), two pull-down FETs (Q3 and Q4)
LATCH
WRITE
READ
READ
BUS
PIN
Table XXV. Port 3, Alternate Pin Functions
Figure 41. Port 3 Bit Latch and I/O Buffer
Alternate Function
RxD (UART Input Pin)
(or Serial Data I/O in Mode 0)
TxD (UART Output Pin)
(or Serial Clock Output in Mode 0)
INT0 (External Interrupt 0)
INT1 (External Interrupt 1)
T0 (Timer/Counter 0 External Input)
PWMCLK (PWM External Clock)
T1 (Timer/Counter 1 External Input)
WR (External Data Memory Write Strobe)
RD (External Data Memory Read Strobe)
2
C mode (SPE = 0), the strong pull-up FET
2
LATCH
D
CL
C operation.
Q
Q
ALTERNATE
ALTERNATE
FUNCTION
FUNCTION
OUTPUT
INPUT
DV
DD
INTERNAL
PULL-UP*
*SEE FIGURE 38
FOR DETAILS OF
INTERNAL PULL-UP
2
C pins (SCLOCK
P3.x
PIN
2
C hard-
REV. A