EZ80F91AZA50SG Zilog, EZ80F91AZA50SG Datasheet - Page 120
EZ80F91AZA50SG
Manufacturer Part Number
EZ80F91AZA50SG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91AZA50SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4564
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS027001-0707
Flash Column Select Register
The Flash Column Select Register is an 8-bit value used to define one of the 256 bytes of
Flash memory contained in a single row. This register is used for all I/O access to Flash
memory. In addition, each access to the FLASH_DATA register causes an autoincrement
of the Flash address stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW,
FLASH_COL). See
Table 45. Flash Column Select Register
Flash Program Control Register
The Flash Program Control Register is used to perform the functions of MASS ERASE,
PAGE ERASE, and ROW PROGRAM. MASS ERASE and PAGE ERASE are
self-clearing functions.
MASS ERASE requires approximately 200 ms to completely erase the full 256 KB of
main Flash and the 512-byte information page if the FLASH_PAGE register(0x00FC)
bit7(INFO_EN) is set. The 200 ms time is not reduced by excluding the 512 byte
information page.
PAGE ERASE requires approximately 10 ms to erase a 2 KB page.
On completion of either a MASS ERASE or PAGE ERASE, the value of each
corresponding bit is reset to 0.
When Flash is being erased, any Read or Write access to Flash forces the CPU into a Wait
state until the Erase operation is complete and the Flash is accessed. Reads and Writes to
areas other than Flash memory proceeds as usual while an Erase operation is
underway.
During row programming, any reads of Flash memory force a WAIT condition until the
row programming operation completes or times out. See
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only.
Bit
Position
[7:0]
FLASH_COL
Value
00h–FFh Column address of Flash memory to be used during an I/O
Table
R/W
45.
7
0
Description
access of Flash memory.
R/W
6
0
R/W
5
0
(FLASH_COL = 00FEh)
R/W
4
0
Table
R/W
3
0
46.
Product Specification
R/W
2
0
eZ80F91 ASSP
R/W
1
0
Flash Memory
R/W
0
0
112
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