EZ80F91AZA50SG Zilog, EZ80F91AZA50SG Datasheet - Page 60
EZ80F91AZA50SG
Manufacturer Part Number
EZ80F91AZA50SG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91AZA50SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4564
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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eZ80F91 ASSP
Product Specification
52
function, PC5 drives the DSR1 signal to UART1. As this signal is Low level true, the
DSR1 signal to UART1 is driven to 1 when PC5 is not in alternate mode function.
GPIO Mode 8—Level Sensitive Interrupt
The port pin is configured for level-sensitive interrupt mode. The value in the Port x Data
register determines if a low or high-level causes an interrupt request. An interrupt request
is generated when the level at the pin is the same as the level stored in the Port x Data
register. The port pin value is sampled by the system clock. The input pin must be held at
the selected interrupt level for a minimum of two system clock periods to initiate an
interrupt. The interrupt request remains active as long as this condition is maintained at the
external source. For example, if a port pin is configured as a low-level-sensitive interrupt,
the interrupt request will be asserted when the pin has been low for two system clocks and
remains active until the pin goes high.
Configuring a pin for mode 8 requires a transition through mode 9 (edge triggered mode).
To avoid the possibility of an unwanted interrupt while transition through mode 9, the
following steps must be taken to select mode 8 when starting from the default mode (mode
2):
1. Disable interrupts
2. Set Px_DR = 0 (low level interrupt) or 1 (high level interrupt)
3. Set Px_ALT2 = 1
4. Set Px_ALT1 =1 (mode 9)
5. Set Px_DDR = 0 (mode 8)
6. Set Px_ALT0 = 1 (to clear possible mode 9 interrupt)
7. Enable interrupts
GPIO Mode 9—Edge Triggered Interrupt
The port pin is configured for single edge triggered interrupt mode. The value in the Port x
Data register determines whether a positive or negative edge causes an interrupt request.
Writing 0 to the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. Writing 1 to the Port x Data register bit sets the selected pin to
generate an interrupt request for rising edges. The interrupt request remains active until 1
is written to the corresponding bit of the Port x Alternate register 0. To select mode 9 from
the default mode (mode 2), you must:
1. Set the Port x Data register
2. Set Px_ALT2 = 1
3. Set Px_ALT1 = 1
4. Set Px_DDR=1
PS027001-0707
General Purpose Input/Output
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