EZ80F91AZA50SG Zilog, EZ80F91AZA50SG Datasheet - Page 59
EZ80F91AZA50SG
Manufacturer Part Number
EZ80F91AZA50SG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91AZA50SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4564
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS027001-0707
GPIO Mode 3—Open Drain
The port pin is configured as open-drain Input/Output. The GPIO pins do not feature an
internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN mode,
an external pull-up resistor must connect the pin to the supply voltage. Writing 0 to the
Port x Data register outputs a Low at the pin. Writing 1 to the Port x Data register results in
high-impedance output.
GPIO Mode 4—Open Source
The port pin is configured as open-source I/O. The GPIO pins do not feature an internal
pull-down to the supply ground. To employ the GPIO pin in OPEN-SOURCE mode, an
external pull-down resistor must connect the pin to the supply ground. Writing 1 to the
Port x Data register outputs a High at the pin. Writing 0 to the Port x Data register results
in a high-impedance output.
GPIO Mode 5
This mode produces a high-impedance output.
GPIO Mode 6
The port pin is configured for dual edge-triggered interrupt mode. Both a rising and a
falling edge on this pin cause an interrupt request to be sent to the CPU. To select this
mode from the default mode (mode 2), you must:
1. Set Px_DR=1
2. Set Px_ALT2=1
3. Set Px_ALT1=0
4. Set Px_DDR=0
Writing a 1 to the Port x ALT0 register bit position corresponding to the interrupt request
clears the interrupt.
GPIO Mode 7—Alternate Functions
The port pin is configured to pass control over to the alternate (secondary) functions
assigned to the pin. For example, the alternate mode function for PC5 is the DSR1 input
signal to UART1 and the alternate mode function for PB4 is the timer 3 input capture.
When GPIO mode 7 is enabled, the pin output data and pin high-impedance control is
obtained from the alternate function's data output and high-impedance control,
respectively. The value in the Port x Data register produces no effect on operation. Input
signals are sampled by the system clock before being passed to the alternate input
function.
If the alternate function of a pin is an input and alternate function mode for that pin is not
enabled, the input is driven to a default non-asserted value. For example, in alternate mode
—
—
Reserved
Dual Edge Triggered
General Purpose Input/Output
Product Specification
eZ80F91 ASSP
51
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