ST10F269Z2Q3 STMicroelectronics, ST10F269Z2Q3 Datasheet - Page 161

• Manufacturer Part Number: ST10F269Z2Q3
• Description: IC FLASH MEM 256KBIT 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 0.3 V to 4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Cpu Family: ST10
• Device Core Size: 16b
• Frequency (max): 40MHz
• Total Internal Ram Size: 12KB
• # I/os (max): 111
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC/RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-2042

ST10F269
Table 48 : Demultiplexed Bus Characteristics (PQFP144 devices)
Notes: 1. RW-delay and
V
ALE cycle time = 4 TCL + 2t
refer to the next following bus cycle.
Table 49 : Demultiplexed Bus Characteristics (TQFP144 devices)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
41
82
83
46
47
48
49
50
51
53
68
55
57
5
6
80
DD
Symbol
= 5V
CC
CC
CC
SR
SR
CC
CC
CC
SR
SR
SR
CC
CC
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes before the end of RD have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
CC
CC
CC
Latched CS hold after RD, WR
Address setup to RdCS, WrCS
(with RW-delay)
Address setup to RdCS, WrCS
(no RW-delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
10%, V
ALE high time
Address setup to ALE
Address/Unlatched CS setup
to RD, WR
(with RW-delay)
t
A
SS
Parameter
refer to the next following bus cycle.
Parameter
= 0V, T
A
A
+ t
= -40 to +85°C, C
C
+ t
F
3
3
(125ns at 32MHz CPU clock without wait states) RW-delay and t
14.5 + 2t
Minimum
21.25 + 2t
15.5 + t
-8.5 + t
5.625 + t
0.625 + t
Maximum CPU Clock
Minimum
2 + 2t
28 + t
10 + t
Maximum CPU Clock =
2 + t
2 + t
–
–
0
–
–
F
F
A
C
C
= 40MHz
F
C
L
A
A
A
= 50pF,
32MHz
A
Maximum
16.5 + t
16.5 + t
4 + t
Maximum
4 + t
–
–
–
–
–
–
–
–
–
C
F
–
–
–
C
F
TCL - 10.5 + 2t
3 TCL - 9.5 + t
2 TCL - 15 + t
TCL - 10.5 + t
TCL - 10.5 + t
2 TCL - 10.5 +
2 TCL - 9.5
2TCL - 10 + 2t
Minimum
-8.5 + t
TCL - 10+ t
TCL - 15+ t
Minimum
+ t
1/2 TCL = 1 to 40MHz
2t
Variable CPU Clock
–
–
0
–
–
1/2 TCL = 1 to 32MHz
A
C
Variable CPU Clock
F
C
F
F
C
A
A
A
A
2 TCL - 8.5 + t
2 TCL - 21 + t
3 TCL - 21 + t
TCL - 8.5 + t
Maximum
Maximum
–
–
–
–
–
–
–
–
–
–
–
–
F
C
C
F
161/184
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A