C8051F305-GS Silicon Laboratories Inc, C8051F305-GS Datasheet - Page 20

• Manufacturer Part Number: C8051F305-GS
• Description: IC 8051 MCU 2K FLASH 14-SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F305-GS

• Program Memory Type: FLASH
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SMBus/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F300DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1444 - ADAPTER PROGRAM TOOLSTICK F300
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1540-5

C8051F300/1/2/3/4/5
Perhaps the most unique Port I/O enhancement is the Digital Crossbar. This is essentially a digital switch-
ing network that allows mapping of internal digital system resources to Port I/O pins (See Figure 1.7). On-
chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the control-
ler can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows
the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular
application.
1.5.
The C8051F300/1/2/3/4/5 Family includes an SMBus/I
baud rate configuration. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
20
Highest
Priority
Lowest
Priority
Serial Ports
SYSCLK
Outputs
SMBus
T0, T1
UART
CP0
PCA
Port Latch
2
2
2
4
2
Figure 1.7. Digital Crossbar Diagram
P0
(P0.0-P0.7)
8
Rev. 2.9
XBR2 Registers
XBR0, XBR1,
Crossbar
Decoder
2
Priority
Digital
C interface and a full-duplex UART with enhanced
8
P0MDIN Registers
P0MDOUT,
Cells
I/O
P0
P0.0
P0.7