C8051F310-GQ Silicon Laboratories Inc, C8051F310-GQ Datasheet - Page 178

• Manufacturer Part Number: C8051F310-GQ
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F31xr

Specifications of C8051F310-GQ

• Core Size: 8-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: 8051
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 1280Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 5
• Digital Ic Case: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1445 - ADAPTER PROGRAM TOOLSTICK F310336-1329 - KIT REF DESIGN SENSORLESS BLDC336-1253 - DEV KIT FOR C8051F310/F311
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1252

C8051F310/1/2/3/4/5
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to
“13.1. Priority Crossbar Decoder” on page 121
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 17.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 8.11. “IT01CF: INT0/INT1
Configuration” on page 93.). Setting GATE0 to ‘1’ allows the timer to be controlled by the external input sig-
nal /INT0 (see
measurements.
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 8.11. “IT01CF: INT0/INT1 Configuration” on page 93.).
178
X = Don't Care
TR0
0
1
1
1
/INT0
T0
GATE0
Crossbar
Section “8.3.5. Interrupt Register Descriptions” on page
X
0
1
1
Pre-scaled Clock
SYSCLK
IN0PL
/INT0
Figure 17.1. T0 Mode 0 Block Diagram
GATE0
X
X
0
1
XOR
Counter/Timer
TR0
0
1
M
Disabled
Disabled
T
H
3
Enabled
Enabled
M
T
3
L
CKCON
M
T
H
2
T
M
2
L
0
1
T
M
1
M
T
0
Rev. 1.5
S
C
A
1
for information on selecting and configuring external I/O
S
C
A
0
G
A
T
E
1
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
TL0
N
P
1
L
I
N
1
S
L
2
I
INT01CF
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
(8 bits)
TH0
N
0
S
L
2
I
N
0
S
L
1
I
N
S
0
L
0
I
89), facilitating pulse width
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
Interrupt
Section