MCHC908JW32FC Freescale Semiconductor, MCHC908JW32FC Datasheet - Page 199
![IC MCU 32K FLASH 8MHZ 48-QFN](/photos/12/17/121792/mchc908jw32fc_sml.jpg)
MCHC908JW32FC
Manufacturer Part Number
MCHC908JW32FC
Description
IC MCU 32K FLASH 8MHZ 48-QFN
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.RD3152MMA7260Q.pdf
(232 pages)
Specifications of MCHC908JW32FC
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, USB
Peripherals
LED, LVD, POR, PWM
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-QFN
Controller Family/series
HC08
No. Of I/o's
29
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SPI, USB
Rohs Compliant
Yes
Processor Series
HC08JW
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USB
Number Of Programmable I/os
29
Number Of Timers
2
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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16.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
16.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG).
16.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register
(CONFIG).
COPRS — COP Rate Select Bit
COPD — COP Disable Bit
16.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
16.5 Interrupts
The COP does not generate CPU interrupt requests.
Freescale Semiconductor
COPRS selects the COP timeout period. Reset clears COPRS.
COPD disables the COP module.
1 = COP timeout period is (8176) × CGMRCLK cycles
0 = COP timeout period is (262,128) × CGMRCLK cycles
1 = COP module disabled
0 = COP module enabled
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
COPRS
$FFFF
$001F
Bit 7
Bit 7
0
Figure 16-2. Configuration Register (CONFIG)
Figure 16-3. COP Control Register (COPCTL)
= Unimplemented
LVISTOP
6
0
6
MC68HC908JW32 Data Sheet, Rev. 6
LVIRSTD
5
0
5
Low byte of reset vector
LVIPWRD
Unaffected by reset
Clear COP counter
4
0
4
3
0
3
SSREC
2
0
2
STOP
1
0
1
COP Control Register
COPD
Bit 0
Bit 0
0
199
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