MCHC908JW32FC Freescale Semiconductor, MCHC908JW32FC Datasheet - Page 208
![IC MCU 32K FLASH 8MHZ 48-QFN](/photos/12/17/121792/mchc908jw32fc_sml.jpg)
MCHC908JW32FC
Manufacturer Part Number
MCHC908JW32FC
Description
IC MCU 32K FLASH 8MHZ 48-QFN
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.RD3152MMA7260Q.pdf
(232 pages)
Specifications of MCHC908JW32FC
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, USB
Peripherals
LED, LVD, POR, PWM
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-QFN
Controller Family/series
HC08
No. Of I/o's
29
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SPI, USB
Rohs Compliant
Yes
Processor Series
HC08JW
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USB
Number Of Programmable I/os
29
Number Of Timers
2
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (3Mb)
Break Module (BRK)
BRKE — Break Enable Bit
BRKA — Break Active Bit
18.5.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
18.5.3 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait
mode. This register is used only in emulation mode.
208
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic
0 to bit 7. Reset clears the BRKE bit.
This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to
BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
1 = (When read) Break address match
0 = (When read) No break address match
Note: Writing a logic 0 clears SBSW.
Address:
Address:
Address:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
$FE0C
$FE0D
$FE00
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Figure 18-6. SIM Break Status Register (SBSR)
R
0
0
Figure 18-4. Break Address Register High (BRKH)
Figure 18-5. Break Address Register Low (BRKL)
14
R
6
0
6
6
0
6
MC68HC908JW32 Data Sheet, Rev. 6
13
R
R
5
0
5
5
0
5
= Reserved
12
R
4
0
4
4
0
4
11
R
3
0
3
3
0
3
10
R
2
0
2
2
0
2
SBSW
Note
1
9
0
1
1
0
1
0
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
R
0
0
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