HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 103

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.2.26 (3) DIVXS
DIVXS instruction, Division by Zero, and Overflow
Since the DIVXS instruction does not detect division by zero or overflow, applications should
detect and handle division by zero and overflow using techniques similar to those used in the
following program.
1. Programming solution for DIVXS.B R0L, R1
Example 1: Convert dividend and divisor to non-negative numbers, then use DIVXU
programming solution for zero divide and overflow
L1: MOV.W
L2: MOV.B
L3: BTST
L4: RTS
ZERODIV:
DIVXS (DIVide eXtend as Signed)
MOV.B
BEQ
ANDC
BPL
NEG.B
ORC
BPL
NEG.W
XORC
EXTU.W
DIVXU.B
MOV.B
DIVXU.B
MOV.B
MOV.B
STC
BTST
BEQ
NEG.B
BEQ
NEG.W
R0L, R0L
ZERODIV
#AF, CCR
L1
R0L
#10, CCR
R1.R1
L2
R1
#50, CCR
R1H, R2L
R2
R0L, R2
R2H, R1H
R0L, R1
R2L, R2H
R1L, R2L
CCR, R1L
#6, R1L
L3
R1H
#4, R1L
L4
R2
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Test divisor
Branch to ZERODIV if R0L = 0
Clear CCR user bits (bits 6 and 4) to 0
Branch to L1 if N flag = 0 (positive divisor)
Take 2’s complement of R0L to make sign positive
Set CCR bit 4 to 1
Test dividend
Branch to L2 if N flag = 0 (positive dividend)
Take 2’s complement of R1 to make sign positive
Invert CCR bits 6 and 4
Use DIVXU.B instruction to divide non-negative dividend
by positive divisor
16 bits ÷ 8 bits
(See DIVXU Instruction, Zero Divide, and Overflow)
Copy CCR contents to R1L
Test CCR bit 6
Branch to L3 if bit 6 = 1
Take 2’s complement of R1H to make sign of remainder negative
Test CCR bit 4
Branch to L4 if bit 4 = 1
Take 2’s complement of R2 to make sign of quotient negative
Zero-divide handling routine
quotient (16 bits) and remainder (8 bits)
Rev. 3.00 Dec 13, 2004 page 87 of 258
Section 2 Instruction Descriptions
REJ09B0213-0300
Divide Signed