HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 249

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.8
Table 2.10 indicates the bus cycles during instruction execution by the H8/300H CPU. For the
number of states per bus cycle, see table 2.7, Number of States per Cycle.
How to read the table:
Legend
R:B
R:W
W:B
W:W
2nd
3rd
4th
5th
NEXT
EA
VEC
JMP @aa:24
Instruction
Bus Cycles During Instruction Execution
Byte-size read
Word-size read
Byte-size write
Address of 2nd word (3rd and 4th bytes)
Address of 4th word (7th and 8th bytes)
Word-size write
Address of 3rd word (5th and 6th bytes)
Address of 5th word (9th and 10th bytes)
Address of next instruction
Effective address
Vector address
R:W 2nd
1
Internal operation
(2 states)
2
R:W EA
3
4
Rev. 3.00 Dec 13, 2004 page 233 of 258
Order of bus cycles
End of instruction
Read effective address (word-size read)
No read or write
Read 2nd word of current instruction
(word-size read)
5
Section 2 Instruction Descriptions
6
REJ09B0213-0300
7
8