MC9S12XEP100CAG Freescale Semiconductor, MC9S12XEP100CAG Datasheet - Page 125

• Manufacturer Part Number: MC9S12XEP100CAG
• Description: IC MCU 16BIT 1M FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24-ch x 12-bit
• Cpu Family: HCS12X
• Device Core Size: 16b
• Frequency (max): 50MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 25
• Operating Supply Voltage (typ): 1.8/2.8/5V
• Operating Supply Voltage (max): 1.98/2.9/5.5V
• Operating Supply Voltage (min): 1.72/2.7/3.13V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
2.3.21
Freescale Semiconductor
Function
Address 0x0240
Write: Anytime.
DDRK
Altern.
Field
Field
Reset
PTT
PTT
PTT
7-0
7-6
4-0
5
W
R
Port K Data Direction—
This register controls the data direction of pins 7 through 0.
The external bus function controls the data direction for the associated pins. In this case the data direction bits will
not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
Port T general purpose input/output data—Data Register
Port T pins 7 through 0 are associated with ECT channels IOC7 and IOC6.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port T general purpose input/output data—Data Register
Port T pins 5 is associated with ECT channel IOC5 and the VREG_API output.
The ECT function takes precedence over the VREG_API and the general purpose I/O function if the related channel
is enabled.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port T general purpose input/output data—Data Register
Port T pins 4 through 0 are associated with ECT channels IOC4 through IOC0.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
PTT7
IOC7
Port T Data Register (PTT)
—
0
7
PTT6
IOC6
—
0
6
Table 2-19. DDRK Register Field Descriptions
Table 2-20. PTT Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-19. Port T Data Register (PTT)
VREG_API
PTT5
IOC5
0
5
PTT4
IOC4
—
0
4
Description
Description
PTT3
IOC3
—
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PTT2
IOC2
—
0
2
Access: User read/write
PTT1
IOC1
—
0
1
PTT0
IOC0
—
0
0
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