MC9S12XEP100CAG Freescale Semiconductor, MC9S12XEP100CAG Datasheet - Page 310

• Manufacturer Part Number: MC9S12XEP100CAG
• Description: IC MCU 16BIT 1M FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24-ch x 12-bit
• Cpu Family: HCS12X
• Device Core Size: 16b
• Frequency (max): 50MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 25
• Operating Supply Voltage (typ): 1.8/2.8/5V
• Operating Supply Voltage (max): 1.98/2.9/5.5V
• Operating Supply Voltage (min): 1.72/2.7/3.13V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8 S12X Debug (S12XDBGV3) Module
8.1.5
8.2
The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the
mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation
modes only.
8.3
8.3.1
A summary of the registers associated with the S12XDBG sub-block is shown in
descriptions of the registers and bits are given in the subsections that follow.
310
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
(See DUG)
(See DUG)
(See DUG)
Pin Name
TAGHITS
EXTERNAL TAGHI / TAGLO
XGATE S/W BREAKPOINT REQUEST
SECURE
CPU12X BUS
XGATE BUS
TAGLO
TAGLO
TAGHI
READ TRACE DATA (DBG READ DATA BUS)
External Signal Description
Memory Map and Registers
Block Diagram
Module Memory Map
Tagging Enable
Pin Functions
Unconditional
Table 8-4. External System Pins Associated With S12XDBG
TAGLO
TAGHI
COMPARATOR A
COMPARATOR B
COMPARATOR C
COMPARATOR D
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 8-1. Debug Module Block Diagram
When instruction tagging is on, tags the high half of the instruction word being
read into the instruction queue.
When instruction tagging is on, tags the low half of the instruction word being
read into the instruction queue.
In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the
end of reset enables the Unconditional Tagging function.
MATCH0
MATCH1
MATCH2
MATCH3
CONTROL
TRIGGER
LOGIC
TAG &
Description
TRIGGER
STATE
BREAKPOINT REQUESTS
CPU12X & XGATE
STATE SEQUENCER
Table
TRACE BUFFER
TAGS
Freescale Semiconductor
STATE
8-2. Detailed
TRACE
CONTROL
TRIGGER