MC9S12XDT512MAA Freescale Semiconductor, MC9S12XDT512MAA Datasheet - Page 1003

• Manufacturer Part Number: MC9S12XDT512MAA
• Description: IC MCU 512K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT512MAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDRS[7:0]
RDRS[7:0]
Reset
Reset
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins.
The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if
the SCI receive channel is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is
disabled.
Field
24.0.5.22 Port S Reduced Drive Register (RDRS)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port S output pin as either full or reduced. If the
port is used as input this bit is ignored.
Field
24.0.5.23 Port S Pull Device Enable Register (PERS)
Read: Anytime.
7–0
7–0
W
W
R
R
RDRS7
PERS7
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Reduced Drive Port S
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
7
0
7
1
on PTS or PTIS registers, when changing the DDRS register.
RDRS6
PERS6
Figure 24-25. Port S Pull Device Enable Register (PERS)
0
1
6
6
Figure 24-24. Port S Reduced Drive Register (RDRS)
Table 24-23. DDRS Field Descriptions
Table 24-24. RDRS Field Descriptions
RDRS5
PERS5
5
0
5
1
RDRS4
PERS4
0
1
4
4
Description
Description
RDRS3
PERS3
3
0
3
1
RDRS2
PERS2
0
1
2
2
RDRS1
PERS1
1
0
1
1
RDRS0
PERS0
0
1
0
0