MC9S12XDT512MAA Freescale Semiconductor, MC9S12XDT512MAA Datasheet - Page 1006

• Manufacturer Part Number: MC9S12XDT512MAA
• Description: IC MCU 512K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT512MAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.27 Port M Input Register (PTIM)
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can also be used to detect
overload or short circuit conditions on output pins.
24.0.5.28 Port M Data Direction Register (DDRM)
Read: Anytime.
Write: Anytime.
This register configures each port M pin as either input or output.
The CAN forces the I/O state to be an output for each port line associated with an enabled output
(TXCAN). It also forces the I/O state to be an input for each port line associated with an enabled input
(RXCAN). In those cases the data direction bits will not change.
1008
PTM[3:2]
PTM[1:0]
Reset
Reset
Field
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
3–2
1–0
W
associated pin values.
W
R
R
1
DDRM7
PTIM7
The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed SPI0 and the general
purpose I/O function if the routed CAN0 module is enabled. Refer to MSCAN section for details.
The routed SPI0 function (SS0 and MISO0) takes precedence of the general purpose I/O function if the routed
SPI0 is enabled and not in bidirectional mode. Refer to SPI section for details.
The CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if the CAN0
module is enabled. Refer to MSCAN section for details.
—
0
7
7
= Unimplemented or Reserved
DDRM6
PTIM6
—
0
6
6
Figure 24-30. Port M Data Direction Register (DDRM)
Table 24-28. PTM Field Descriptions (continued)
Figure 24-29. Port M Input Register (PTIM)
DDRM5
MC9S12XDP512 Data Sheet, Rev. 2.21
PTIM5
—
0
5
5
DDRM4
PTIM4
—
0
4
4
Description
DDRM3
PTIM3
—
0
3
3
DDRM2
PTIM2
—
0
2
2
DDRM1
Freescale Semiconductor
PTIM1
—
0
1
1
DDRM0
PTIM0
—
0
0
0