MC9S12XDT512MAA Freescale Semiconductor, MC9S12XDT512MAA Datasheet - Page 611

• Manufacturer Part Number: MC9S12XDT512MAA
• Description: IC MCU 512K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT512MAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.5.3
16.5.3.1
Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking
the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualified to wake
up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode:
An XIRQ request can wake up the MCU from stop or wait mode at anytime, even if the X bit in CCR is set.
16.5.3.2
Interrupt request channels which are configured to be handled by the XGATE are capable of waking up the
XGATE. Interrupt request channels handled by the XGATE do not affect the state of the CPU.
Freescale Semiconductor
Processing Levels
•
•
•
If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU.
An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the
current IPL in CCR.
I bit maskable interrupt requests which are configured to be handled by the XGATE are not capable
of waking up the CPU.
Stacked IPL
IPL in CCR
Wake Up from Stop or Wait Mode
CPU Wake Up from Stop or Wait Mode
XGATE Wake Up from Stop or Wait Mode
7
6
5
4
3
2
1
0
Reset
0
Figure 16-14. Interrupt Processing Example
MC9S12XDP512 Data Sheet, Rev. 2.21
L4
0
4
L7
0
4
7
L1 (Pending)
L3 (Pending)
RTI
0
4
RTI
0
3
Chapter 16 Interrupt (S12XINTV1)
RTI
0
1
RTI
0
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