HD64F7145F50V Renesas Electronics America, HD64F7145F50V Datasheet - Page 485
![IC SUPERH MCU FLASH 256K 144QFP](/photos/12/22/122200/hd64f7145f50v_sml.jpg)
HD64F7145F50V
Manufacturer Part Number
HD64F7145F50V
Description
IC SUPERH MCU FLASH 256K 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7145F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 485 of 932
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13.5.1
Figure 13.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Multiprocessor Serial Data Transmission
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart
Write transmit data to TDR and
as an output port with the PFC
Clear TE bit in SCR to 0;
Read TDRE flag in SSR
Read TEND flag in SSR
set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Start transmission
select the TxD pin
Break output?
Clear DR to 0
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
[1] SCI initialization:
[2] SCI status check and transmit
[3] Serial transmission continuation
[4] Break output at the end of serial
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 439 of 882
Set the TxD pin using the PFC.
After the TE bit is set to 1, a
frame period of 1s is output, and
transmission is enabled. This
action doesn't initiate immediate
data transmission.
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DMAC or DTC is activated by a
transmit data empty interrupt
(TXI) request, and data is written
to TDR.
transmission:
To output a break in serial
transmission, first clear the port
data register (DR) to 0, then
clear the TE bit to 0 in SCR and
REJ09B0108-0400
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