HD64F7145F50V Renesas Electronics America, HD64F7145F50V Datasheet - Page 84
![IC SUPERH MCU FLASH 256K 144QFP](/photos/12/22/122200/hd64f7145f50v_sml.jpg)
HD64F7145F50V
Manufacturer Part Number
HD64F7145F50V
Description
IC SUPERH MCU FLASH 256K 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7145F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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2. CPU
• Arithmetic Operation Instructions
Rev.4.00 Mar. 27, 2008 Page 38 of 882
REJ09B0108-0400
Instruction
ADD
ADD
ADDC
ADDV
CMP/EQ
CMP/EQ
CMP/HS
CMP/GE
CMP/HI
CMP/GT
CMP/PL
CMP/PZ
CMP/STR Rm,Rn
DIV1
DIV0S
DIV0U
DMULS.L Rm,Rn
DMULU.L Rm,Rn
Rm,Rn
#imm,Rn 0111nnnniiiiiiii
Rm,Rn
Rm,Rn
#imm,R0 10001000iiiiiiii
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rn
Rn
Rm,Rn
Rm,Rn
Instruction Code
0011nnnnmmmm1100
0011nnnnmmmm1110
0011nnnnmmmm1111
0011nnnnmmmm0000
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010101
0100nnnn00010001
0010nnnnmmmm1100
0011nnnnmmmm0100
0010nnnnmmmm0111
0000000000011001
0011nnnnmmmm1101
0011nnnnmmmm0101
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn, Carry
→ T
Rn + Rm → Rn, Overflow
→ T
If R0 = imm, 1 → T
If Rn = Rm, 1 → T
If Rn≥Rm with unsigned
data, 1 → T
If Rn ≥ Rm with signed
data, 1 → T
If Rn > Rm with
unsigned data, 1 → T
If Rn > Rm with signed
data, 1 → T
If Rn > 0, 1 → T
If Rn ≥ 0, 1 → T
If Rn and Rm have an
equivalent byte, 1 → T
Single-step division
(Rn ÷ Rm)
MSB of Rn → Q, MSB
of Rm → M, M ^ Q → T
0 → M/Q/T
Signed operation of Rn
× Rm → MACH, MACL
32 × 32 → 64 bits
Unsigned operation of
Rn × Rm → MACH, MACL
32 × 32 → 64 bits
Execution
States
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2 to 4*
2 to 4*
T Bit
—
—
Carry
Overflow
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Calculation
result
Calculation
result
0
—
—
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