HD64F7145F50V Renesas Electronics America, HD64F7145F50V Datasheet - Page 56
![IC SUPERH MCU FLASH 256K 144QFP](/photos/12/22/122200/hd64f7145f50v_sml.jpg)
HD64F7145F50V
Manufacturer Part Number
HD64F7145F50V
Description
IC SUPERH MCU FLASH 256K 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7145F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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1. Overview
Rev.4.00 Mar. 27, 2008 Page 10 of 882
REJ09B0108-0400
Type
Bus control
Direct
memory
access
controller
(DMAC)
Symbol
CS3 to CS0
CS5, CS4
(SH7145
masked ROM
version and
ROM less
version only)
CS7, CS6
(masked
ROM version
and ROM
less version
only)
RD
WRHH
(SH7145
only)
WRHL
(SH7145
only)
WRH
WRL
WAIT
DREQ0,
DREQ1
DRAK0,
DRAK1
DACK0,
DACK1
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Name
Chip select
3 to 0
Chip select
5, 4
Chip select
7, 6
Read
Write HH
Write HL
Write
upper half
Write lower
half
Wait
DMA transfer
request
DREQ request
acknowledge
DMA transfer
strobe
Function
Chip select signal for external memory or
devices.
Shows reading from external devices.
Shows writing into the HH 8 bits (bits 31 to
24) of the external data.
Shows writing into the HL 8 bits (bits 23 to
16) of the external data.
Shows writing into the upper 8 bits (bits 15
to 8) of the external data.
Shows writing into the lower 8 bits (bit7 to
bit0) of the external data.
Inserts the wait cycles into the bus cycle
when accessing the external spaces.
DMA request input pins from an external
device.
Outputs an acknowledge signal to the
external device that has input a DMA
transfer request signal.
Outputs a strobe to the I/O of the external
device that has input a DMA transfer
request signal.
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