HD64F7145F50V Renesas Electronics America, HD64F7145F50V Datasheet - Page 777
![IC SUPERH MCU FLASH 256K 144QFP](/photos/12/22/122200/hd64f7145f50v_sml.jpg)
HD64F7145F50V
Manufacturer Part Number
HD64F7145F50V
Description
IC SUPERH MCU FLASH 256K 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7145F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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24.4
24.4.1
When a transition is made to software standby mode while the port high-impedance bit (HIZ) in
SBYCR is 0, I/O port states are retained. Therefore, there is no reduction in current consumption
for the output current when a high-level signal is output.
24.4.2
Current consumption increases during the oscillation stabilization wait period.
24.4.3
Relevant interrupt operations cannot be performed in module standby mode. Consequently, if the
CPU enters module standby mode while an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DMAC/DTC activation source.
Interrupts should therefore be disabled before entering module standby mode.
24.4.4
MSTCR1 and MSTCR2 should only be written to by the CPU.
24.4.5
In sleep mode, data should not be accessed by the DMAC, DTC, or AUD.
Usage Notes
I/O Port Status
Current Consumption during Oscillation Stabilization Wait Period
On-Chip Peripheral Module Interrupt
Writing to MSTCR1 and MSTCR2
DMAC, DTC, or AUD Operation in Sleep Mode
Rev.4.00 Mar. 27, 2008 Page 731 of 882
24. Power-Down Modes
REJ09B0108-0400
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