MC56F8367VPYE Freescale Semiconductor, MC56F8367VPYE Datasheet - Page 22

IC DSP 16BIT 60MHZ 160-LQFP

MC56F8367VPYE

Manufacturer Part Number
MC56F8367VPYE
Description
IC DSP 16BIT 60MHZ 160-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheets

Specifications of MC56F8367VPYE

Core Processor
56800
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
76
Program Memory Size
544KB (272K x 16)
Program Memory Type
FLASH
Ram Size
18K x 16
Voltage - Supply (vcc/vdd)
2.25 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
160-LQFP
Cpu Family
56F8xxx
Device Core Size
16b
Frequency (max)
60MHz
Interface Type
CAN/SCI/SPI
Total Internal Ram Size
36KB
# I/os (max)
76
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
4(4-chx12-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
160
Package Type
LQFP
Data Bus Width
16 bit
Processor Series
MC56F83xx
Core
56800E
Numeric And Arithmetic Format
Fixed-Point
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
76
Data Ram Size
36 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MC56F8367EVME
Minimum Operating Temperature
- 40 C
Package
160LQFP
Family Name
56F8xxx
Maximum Speed
60 MHz
Number Of Timers
4
For Use With
MC56F8367EVME - EVAL BOARD FOR MC56F83X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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22
(SYS_CLK2)
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
(prescaler_
(oscillator_
(SYS_CLK)
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
Signal
clock)
clock)
Name
(A16)
(A17)
(A18)
(A19)
(A20)
(A21)
(A22)
(A23)
No.
Pin
33
34
35
36
37
46
47
48
Ball No.
M1
M2
N4
M4
P3
L1
L3
L2
Schmitt
Schmitt
Output
Output
Output
Output
Output
Input/
Input/
Type
56F8367 Technical Data, Rev. 8
enabled
enabled
During
pull-up
pull-up
Reset
State
Input,
Input,
Port B GPIO — These four GPIO pins can be programmed as
input or output pins.
Address Bus — A16 - A19 specify one of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A16 - A19 and EMI control signals are tri-stated
when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
After reset, the startup state of GPIOB0 - GPIOB3 (GPIO or
address) is determined as a function of EXTBOOT, EMI_MODE
and the Flash security setting. See
information on when this pin is configured as an address pin at
reset. In all cases, this state may be changed by writing to
GPIOB_PER.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOB_PUR register.
Port B GPIO — These four GPIO pins can be programmed as
input or output pins.
Address Bus — A20 - A23 specify one of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A20–A23 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead
of using the default setting.
Clock Outputs — can be used to monitor the prescaler_clock,
SYS_CLK, SYS_CLK2 or oscillator_clock on GPIOB4 through
GPIOB7, respectively.
After reset, the default state is GPIO.
These pins can also be used to extend the external address bus
to its full length or to view any of several system clocks. In these
cases, the GPIO_B_PER can be used to individually disable the
GPIO. The CLKOSR register in the SIM (see
be used to choose between address and clock functions.
Signal Description
Table 4-4
Freescale Semiconductor
Part
for further
6.5.7) can then
Preliminary

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