M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 218
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122251/m30853fjgp_u3_sml.jpg)
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M
R
R
e
E
3
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J
2
Figure 17.2 U0TB to U4TB Registers and U0RB to U4RB Registers
0
C
1
9
0 .
8 /
B
0
3
5
0
3
G
UARTi Transmit Buffer Register
J
b15
7
u
UARTi Receive Buffer Register
o r
0 -
. l
NOTES:
b15
u
0
1
NOTES:
p
, 1
0
1. Use the MOV instruction to set the UiTB register.
3
(
1. The ABT bit can be set to "0" only.
2. When the SMD2 to SMD0 bits in the UiMR register are set to "000
3. These error flags are disabled when the SMD2 to SMD0 bits are set to "001
2
M
0
the UiC1 register is set to "0" (receive disable), the OER, FER, PER and SUM bits are set to "0".
When all OER, FER and PER bits are set to "0", the SUM bit is set to "0".
Also, the FER and PER bits are set to "0" by reading low-order bits in the UiRB register.
I/O mode) or to "010
3
0
5
2
b8
C
b7
8 /
b8
Page 193
, 5
b7
M
3
2
C
f o
8 /
b0
2
4
b0
5
" (I
9
(b15 - b9)
) T
(b7 - b0)
Symbol
4
(b7 - b0)
(b10 - b9)
2
(b8)
Symbol
Bit
C mode). When read, the contents are indeterminate.
(b8)
OER
SUM
ABT
FER
PER
Symbol
U0TB to U2TB 036B
U3TB, U4TB
Symbol
U0RB to U2RB 036F
U3RB, U4RB
Bit
Transmit data (D
Transmit data (D
Nothing is assigned.
When write, set to "0".
When read, its content is indeterminate.
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Arbitration Lost
Detect Flag
Overrun Error Flag
Framing Error
Flag
Parity Error Flag
Error Sum Flag
(2, 3)
(i=0 to 4)
(i=0 to 4)
Bit Name
Address
032B
Address
032F
(1)
16
16
16-
16-
-
-
036A
032A
036E
032E
(1)
7
8
(2, 3)
)
(2, 3)
to D
16
16
(2)
16,
16,
, 02EB
, 02FB
0
)
Received data (D
0: Not detected (win)
1: Detected (lose)
0: No overrun error occurs
1: Overrun error occurs
Received data (D
0: No framing error occurs
1: Framing error occurs
0: No parity error occurs
1: Parity error occurs
0: No error occurs
1: Error occurs
Function
02EF
02FF
16-
16-
16
16
02EA
02FA
-
-
02EE
02FE
2
" (serial I/O disable) or the RE bit in
16
16
, 033B
16
16,
033F
Function
7
8
)
16-
to D
2
" (clock synchronous serial
033A
16
0
-
)
033E
16
16
After Reset
Indeterminate
Indeterminate
After Reset
Indeterminate
Indeterminate
WO
WO
RW
RW
RW
RO
RO
RO
RO
17. Serial I/O
RO
RO
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